ARM Ltd. MPS3_SSE_200 2025.07.02 ARM 32-bit v8-M Mainline based device CM33 r0p2 little true 4 false 8 32 DUALTIMER Dual Timer Timer 0x40002000 0x0 0x3C registers n DUALTIMER Dual Timer 5 TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF DUALTIMER_Secure Dual Timer (Secure) Timer 0x50002000 0x0 0x3C registers n TIMER1BGLOAD Timer 1 Background Load Register 0x18 read-write n 0x0 0xFFFFFFFF TIMER1CONTROL Timer 1 Control Register 0x8 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER1INTCLR Timer 1 Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER1LOAD Timer 1 Load Register 0x0 read-write n 0x0 0xFFFFFFFF TIMER1MIS Timer 1 Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER1RIS Timer 1 Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER1VALUE Timer 1 Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF TIMER2BGLOAD Timer 2 Background Load Register 0x38 read-write n 0x0 0xFFFFFFFF TIMER2CONTROL Timer 2 Control Register 0x28 read-write n 0x20 0xFFFFFFFF InterruptEnable Interrupt Enable bit. 5 1 Disable Interrupt is disabled. 0 Enable Interrupt is enabled. 1 OneShotCount Selects one-shot or wrapping counter mode. 0 1 Wrapping Wrapping counter mode 0 OneShot One-shot counter mode 1 TimerEnable Timer Enable Enable bit. 7 1 Disable Timer is disabled. 0 Enable Timer is enabled. 1 TimerMode Timer Mode bit. 6 1 Free-Running Free-Running timer mode. 0 Periodic Periodic timer mode. 1 TimerPre Timer prescale bits. 2 2 divided by 1 clock is divided by 1 0 divided by 16 clock is divided by 16 1 divided by 256 clock is divided by 256 2 TimerSize Selects 16-bit or 32- bit counter operation. 1 1 16-bit 16-bit counter mode 0 32-bit 32-bit counter mode 1 TIMER2INTCLR Timer 2 Interrupt Clear Register 0x2C write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear TIMER2LOAD Timer 2 Load Register 0x20 read-write n 0x0 0xFFFFFFFF TIMER2MIS Timer 2 Mask Interrupt Status Register 0x34 read-only n 0x0 0xFFFFFFFF MIS Masked Timer Interrupt 0 1 TIMER2RIS Timer 2 Raw Interrupt Status Register 0x30 read-only n 0x0 0xFFFFFFFF RIS Raw Timer Interrupt 0 1 TIMER2VALUE Timer 2 Value Register 0x24 read-only n 0xFFFFFFFF 0xFFFFFFFF FPGAIO FPGA System Control I/O FPGAIO 0x41302000 0x0 0x100 registers n BUTTON Button Connections 0x8 32 read-write n 0x0 0xFFFFFFFF BUTTON0 0 1 Off BUTTON is off 0 On BUTTON is on 1 BUTTON1 1 2 Off BUTTON is off 0 On BUTTON is on 1 CLK100HZ 100Hz Up Counter 0x14 32 read-only n 0x0 0xFFFFFFFF CLK1HZ 1Hz Up Counter 0x10 32 read-only n 0x0 0xFFFFFFFF COUNTER Cycle up counter 0x18 32 read-write n 0x0 0xFFFFFFFF LED LED Connections 0x0 32 read-write n 0x0 0xFFFFFFFF LED0 0 1 Off LED is off 0 On LED is on 1 LED1 1 2 Off LED is off 0 On LED is on 1 LED2 2 3 Off LED is off 0 On LED is on 1 LED3 3 4 Off LED is off 0 On LED is on 1 LED4 4 5 Off LED is off 0 On LED is on 1 LED5 5 6 Off LED is off 0 On LED is on 1 LED6 6 7 Off LED is off 0 On LED is on 1 LED7 7 8 Off LED is off 0 On LED is on 1 LED8 8 9 Off LED is off 0 On LED is on 1 LED9 9 10 Off LED is off 0 On LED is on 1 MISC Misc. Control 0x4C 32 read-write n 0x0 0xFFFFFFFF ADC_SPI_nCS 0 1 SHIELD0_SPI_nCS 1 2 SHIELD1_SPI_nCS 2 3 PRESCALER Reload value for prescaler counter 0x1C 32 read-write n 0x0 0xFFFFFFFF PSCNTR Prescale Counter 0x20 32 read-write n 0x0 0xFFFFFFFF SWITCH Switches 0x28 32 read-write n 0x0 0xFFFFFFFF SWITCH_0 SWITCH: 0 = OFF 1 = ON 0 1 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_1 SWITCH: 0 = OFF 1 = ON 1 2 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_2 SWITCH: 0 = OFF 1 = ON 2 3 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_3 SWITCH: 0 = OFF 1 = ON 3 4 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_4 SWITCH: 0 = OFF 1 = ON 4 5 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_5 SWITCH: 0 = OFF 1 = ON 5 6 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_6 SWITCH: 0 = OFF 1 = ON 6 7 Off SWITCH is off 0 On SWITCH is on 1 SWITH_7 SWITCH: 0 = OFF 1 = ON 7 8 Off SWITCH is off 0 On SWITCH is on 1 FPGAIO_Secure FPGA System Control I/O (Secure) FPGAIO 0x51302000 0x0 0x100 registers n BUTTON Button Connections 0x8 32 read-write n 0x0 0xFFFFFFFF BUTTON0 0 1 Off BUTTON is off 0 On BUTTON is on 1 BUTTON1 1 2 Off BUTTON is off 0 On BUTTON is on 1 CLK100HZ 100Hz Up Counter 0x14 32 read-only n 0x0 0xFFFFFFFF CLK1HZ 1Hz Up Counter 0x10 32 read-only n 0x0 0xFFFFFFFF COUNTER Cycle up counter 0x18 32 read-write n 0x0 0xFFFFFFFF LED LED Connections 0x0 32 read-write n 0x0 0xFFFFFFFF LED0 0 1 Off LED is off 0 On LED is on 1 LED1 1 2 Off LED is off 0 On LED is on 1 LED2 2 3 Off LED is off 0 On LED is on 1 LED3 3 4 Off LED is off 0 On LED is on 1 LED4 4 5 Off LED is off 0 On LED is on 1 LED5 5 6 Off LED is off 0 On LED is on 1 LED6 6 7 Off LED is off 0 On LED is on 1 LED7 7 8 Off LED is off 0 On LED is on 1 LED8 8 9 Off LED is off 0 On LED is on 1 LED9 9 10 Off LED is off 0 On LED is on 1 MISC Misc. Control 0x4C 32 read-write n 0x0 0xFFFFFFFF ADC_SPI_nCS 0 1 SHIELD0_SPI_nCS 1 2 SHIELD1_SPI_nCS 2 3 PRESCALER Reload value for prescaler counter 0x1C 32 read-write n 0x0 0xFFFFFFFF PSCNTR Prescale Counter 0x20 32 read-write n 0x0 0xFFFFFFFF SWITCH Switches 0x28 32 read-write n 0x0 0xFFFFFFFF SWITCH_0 SWITCH: 0 = OFF 1 = ON 0 1 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_1 SWITCH: 0 = OFF 1 = ON 1 2 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_2 SWITCH: 0 = OFF 1 = ON 2 3 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_3 SWITCH: 0 = OFF 1 = ON 3 4 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_4 SWITCH: 0 = OFF 1 = ON 4 5 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_5 SWITCH: 0 = OFF 1 = ON 5 6 Off SWITCH is off 0 On SWITCH is on 1 SWITCH_6 SWITCH: 0 = OFF 1 = ON 6 7 Off SWITCH is off 0 On SWITCH is on 1 SWITH_7 SWITCH: 0 = OFF 1 = ON 7 8 Off SWITCH is off 0 On SWITCH is on 1 GPIO0 General-purpose I/O 0 GPIO 0x41100000 0x0 0x3C registers n GPIO0 GPIO 0 combined 68 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO0_Secure General-purpose I/O 0 (Secure) GPIO 0x51100000 0x0 0x3C registers n ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO1 General-purpose I/O 1 GPIO 0x41101000 0x0 0x3C registers n GPIO1 GPIO 1 combined 69 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO1_Secure General-purpose I/O 1 (Secure) PORTS 0x51101000 0x0 0x100 registers n HWSEL Port 14 Pin Hardware Select Register 0x74 32 read-write n 0x0 0xFFFFFFFF HW0 Port n Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port n Pin Hardware Select Bit 1 2 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW10 Port n Pin Hardware Select Bit 10 20 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW11 Port n Pin Hardware Select Bit 11 22 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW12 Port n Pin Hardware Select Bit 12 24 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW13 Port n Pin Hardware Select Bit 13 26 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW14 Port n Pin Hardware Select Bit 14 28 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW15 Port n Pin Hardware Select Bit 15 30 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port n Pin Hardware Select Bit 2 4 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port n Pin Hardware Select Bit 3 6 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port n Pin Hardware Select Bit 4 8 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port n Pin Hardware Select Bit 5 10 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port n Pin Hardware Select Bit 6 12 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW7 Port n Pin Hardware Select Bit 7 14 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW8 Port n Pin Hardware Select Bit 8 16 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW9 Port n Pin Hardware Select Bit 9 18 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 IN Port 14 Input Register 0x24 32 read-write n 0x0 0xFFFF0000 P0 Port n Input Bit 0 0 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P1 Port n Input Bit 1 1 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P10 Port n Input Bit 10 10 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P11 Port n Input Bit 11 11 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P12 Port n Input Bit 12 12 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P13 Port n Input Bit 13 13 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P14 Port n Input Bit 14 14 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P15 Port n Input Bit 15 15 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P2 Port n Input Bit 2 2 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P3 Port n Input Bit 3 3 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P4 Port n Input Bit 4 4 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P5 Port n Input Bit 5 5 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P6 Port n Input Bit 6 6 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P7 Port n Input Bit 7 7 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P8 Port n Input Bit 8 8 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P9 Port n Input Bit 9 9 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 IOCR0 Port 14 Input/Output Control Register 0 0x10 32 read-write n 0x0 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC1 Port Control for Port n Pin 0 to 3 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC2 Port Control for Port n Pin 0 to 3 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC3 Port Control for Port n Pin 0 to 3 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR12 Port 14 Input/Output Control Register 12 0x1C 32 read-write n 0x0 0xFFFFFFFF PC12 Port Control for Port n Pin 12 to 15 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC13 Port Control for Port n Pin 12 to 15 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC14 Port Control for Port n Pin 12 to 15 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC15 Port Control for Port n Pin 12 to 15 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR4 Port 14 Input/Output Control Register 4 0x14 32 read-write n 0x0 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 7 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC5 Port Control for Port n Pin 4 to 7 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC6 Port Control for Port n Pin 4 to 7 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC7 Port Control for Port n Pin 4 to 7 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR8 Port 14 Input/Output Control Register 8 0x18 32 read-write n 0x0 0xFFFFFFFF PC10 Port Control for Port n Pin 8 to 11 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC11 Port Control for Port n Pin 8 to 11 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC8 Port Control for Port n Pin 8 to 11 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC9 Port Control for Port n Pin 8 to 11 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 OMR Port 14 Output Modification Register 0x4 32 read-write n 0x0 0xFFFFFFFF PR0 Port n Reset Bit 0 16 write-only PR1 Port n Reset Bit 1 17 write-only PR10 Port n Reset Bit 10 26 write-only PR11 Port n Reset Bit 11 27 write-only PR12 Port n Reset Bit 12 28 write-only PR13 Port n Reset Bit 13 29 write-only PR14 Port n Reset Bit 14 30 write-only PR15 Port n Reset Bit 15 31 write-only PR2 Port n Reset Bit 2 18 write-only PR3 Port n Reset Bit 3 19 write-only PR4 Port n Reset Bit 4 20 write-only PR5 Port n Reset Bit 5 21 write-only PR6 Port n Reset Bit 6 22 write-only PR7 Port n Reset Bit 7 23 write-only PR8 Port n Reset Bit 8 24 write-only PR9 Port n Reset Bit 9 25 write-only PS0 Port n Set Bit 0 0 write-only PS1 Port n Set Bit 1 1 write-only PS10 Port n Set Bit 10 10 write-only PS11 Port n Set Bit 11 11 write-only PS12 Port n Set Bit 12 12 write-only PS13 Port n Set Bit 13 13 write-only PS14 Port n Set Bit 14 14 write-only PS15 Port n Set Bit 15 15 write-only PS2 Port n Set Bit 2 2 write-only PS3 Port n Set Bit 3 3 write-only PS4 Port n Set Bit 4 4 write-only PS5 Port n Set Bit 5 5 write-only PS6 Port n Set Bit 6 6 write-only PS7 Port n Set Bit 7 7 write-only PS8 Port n Set Bit 8 8 write-only PS9 Port n Set Bit 9 9 write-only OUT Port 14 Output Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 Port n Output Bit 0 0 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P1 Port n Output Bit 1 1 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P10 Port n Output Bit 10 10 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P11 Port n Output Bit 11 11 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P12 Port n Output Bit 12 12 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P13 Port n Output Bit 13 13 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P14 Port n Output Bit 14 14 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P15 Port n Output Bit 15 15 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P2 Port n Output Bit 2 2 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P3 Port n Output Bit 3 3 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P4 Port n Output Bit 4 4 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P5 Port n Output Bit 5 5 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P6 Port n Output Bit 6 6 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P7 Port n Output Bit 7 7 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P8 Port n Output Bit 8 8 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P9 Port n Output Bit 9 9 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 PDISC Port 14 Pin Function Decision Control Register 0x60 32 read-write n 0x0 0xFFFF0000 PDIS0 Pad Disable for Port 14 Pin 0 0 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 analog input 0 selected. #1 PDIS1 Pad Disable for Port 14 Pin 1 1 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 analog input 1 selected. #1 PDIS12 Pad Disable for Port 14 Pin 12 12 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 4 selected. #1 PDIS13 Pad Disable for Port 14 Pin 13 13 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 5 selected. #1 PDIS14 Pad Disable for Port 14 Pin 14 14 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 6 selected. #1 PDIS15 Pad Disable for Port 14 Pin 15 15 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 7 selected. #1 PDIS2 Pad Disable for Port 14 Pin 2 2 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 and ADC 1 analog input 2 selected. #1 PDIS3 Pad Disable for Port 14 Pin 3 3 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 and ADC 1 analog input 3 selected. #1 PDIS4 Pad Disable for Port 14 Pin 4 4 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 analog input 4 and ADC 2 analog input 0 and DAC Reference selected. #1 PDIS5 Pad Disable for Port 14 Pin 5 5 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 analog input 5 and ADC 2 analog input 1 selected. #1 PDIS6 Pad Disable for Port 14 Pin 6 6 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 0 analog input 6 selected. #1 PDIS7 Pad Disable for Port 14 Pin 7 7 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC0 analog input 7 selected. #1 PDIS8 Pad Disable for Port 14 Pin 8 8 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 0 and ADC 2 analog input 4 and DAC output 0 selected. #1 PDIS9 Pad Disable for Port 14 Pin 9 9 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 1 analog input 1 and ADC 2 analog input 5 and DAC output 1 selected. #1 PPS Port 14 Pin Power Save Register 0x70 32 read-write n 0x0 0xFFFFFFFF PPS0 Port n Pin Power Save Bit 0 0 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS1 Port n Pin Power Save Bit 1 1 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS10 Port n Pin Power Save Bit 10 10 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS11 Port n Pin Power Save Bit 11 11 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS12 Port n Pin Power Save Bit 12 12 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS13 Port n Pin Power Save Bit 13 13 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS14 Port n Pin Power Save Bit 14 14 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS15 Port n Pin Power Save Bit 15 15 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS2 Port n Pin Power Save Bit 2 2 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS3 Port n Pin Power Save Bit 3 3 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS4 Port n Pin Power Save Bit 4 4 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS5 Port n Pin Power Save Bit 5 5 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS6 Port n Pin Power Save Bit 6 6 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS7 Port n Pin Power Save Bit 7 7 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS8 Port n Pin Power Save Bit 8 8 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS9 Port n Pin Power Save Bit 9 9 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 GPIO2 General-purpose I/O 2 GPIO 0x41102000 0x0 0x3C registers n GPIO2 GPIO 2 combined 70 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO2_Secure General-purpose I/O 2 (Secure) PORTS 0x51102000 0x0 0x100 registers n HWSEL Port 15 Pin Hardware Select Register 0x74 32 read-write n 0x0 0xFFFFFFFF HW0 Port n Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port n Pin Hardware Select Bit 1 2 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW10 Port n Pin Hardware Select Bit 10 20 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW11 Port n Pin Hardware Select Bit 11 22 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW12 Port n Pin Hardware Select Bit 12 24 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW13 Port n Pin Hardware Select Bit 13 26 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW14 Port n Pin Hardware Select Bit 14 28 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW15 Port n Pin Hardware Select Bit 15 30 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port n Pin Hardware Select Bit 2 4 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port n Pin Hardware Select Bit 3 6 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port n Pin Hardware Select Bit 4 8 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port n Pin Hardware Select Bit 5 10 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port n Pin Hardware Select Bit 6 12 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW7 Port n Pin Hardware Select Bit 7 14 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW8 Port n Pin Hardware Select Bit 8 16 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW9 Port n Pin Hardware Select Bit 9 18 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 IN Port 15 Input Register 0x24 32 read-write n 0x0 0xFFFF0000 P0 Port n Input Bit 0 0 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P1 Port n Input Bit 1 1 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P10 Port n Input Bit 10 10 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P11 Port n Input Bit 11 11 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P12 Port n Input Bit 12 12 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P13 Port n Input Bit 13 13 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P14 Port n Input Bit 14 14 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P15 Port n Input Bit 15 15 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P2 Port n Input Bit 2 2 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P3 Port n Input Bit 3 3 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P4 Port n Input Bit 4 4 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P5 Port n Input Bit 5 5 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P6 Port n Input Bit 6 6 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P7 Port n Input Bit 7 7 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P8 Port n Input Bit 8 8 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P9 Port n Input Bit 9 9 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 IOCR0 Port 15 Input/Output Control Register 0 0x10 32 read-write n 0x0 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC1 Port Control for Port n Pin 0 to 3 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC2 Port Control for Port n Pin 0 to 3 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC3 Port Control for Port n Pin 0 to 3 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR12 Port 15 Input/Output Control Register 12 0x1C 32 read-write n 0x0 0xFFFFFFFF PC12 Port Control for Port n Pin 12 to 15 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC13 Port Control for Port n Pin 12 to 15 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC14 Port Control for Port n Pin 12 to 15 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC15 Port Control for Port n Pin 12 to 15 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR4 Port 15 Input/Output Control Register 4 0x14 32 read-write n 0x0 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 7 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC5 Port Control for Port n Pin 4 to 7 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC6 Port Control for Port n Pin 4 to 7 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC7 Port Control for Port n Pin 4 to 7 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR8 Port 15 Input/Output Control Register 8 0x18 32 read-write n 0x0 0xFFFFFFFF PC10 Port Control for Port n Pin 8 to 11 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC11 Port Control for Port n Pin 8 to 11 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC8 Port Control for Port n Pin 8 to 11 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC9 Port Control for Port n Pin 8 to 11 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 OMR Port 15 Output Modification Register 0x4 32 read-write n 0x0 0xFFFFFFFF PR0 Port n Reset Bit 0 16 write-only PR1 Port n Reset Bit 1 17 write-only PR10 Port n Reset Bit 10 26 write-only PR11 Port n Reset Bit 11 27 write-only PR12 Port n Reset Bit 12 28 write-only PR13 Port n Reset Bit 13 29 write-only PR14 Port n Reset Bit 14 30 write-only PR15 Port n Reset Bit 15 31 write-only PR2 Port n Reset Bit 2 18 write-only PR3 Port n Reset Bit 3 19 write-only PR4 Port n Reset Bit 4 20 write-only PR5 Port n Reset Bit 5 21 write-only PR6 Port n Reset Bit 6 22 write-only PR7 Port n Reset Bit 7 23 write-only PR8 Port n Reset Bit 8 24 write-only PR9 Port n Reset Bit 9 25 write-only PS0 Port n Set Bit 0 0 write-only PS1 Port n Set Bit 1 1 write-only PS10 Port n Set Bit 10 10 write-only PS11 Port n Set Bit 11 11 write-only PS12 Port n Set Bit 12 12 write-only PS13 Port n Set Bit 13 13 write-only PS14 Port n Set Bit 14 14 write-only PS15 Port n Set Bit 15 15 write-only PS2 Port n Set Bit 2 2 write-only PS3 Port n Set Bit 3 3 write-only PS4 Port n Set Bit 4 4 write-only PS5 Port n Set Bit 5 5 write-only PS6 Port n Set Bit 6 6 write-only PS7 Port n Set Bit 7 7 write-only PS8 Port n Set Bit 8 8 write-only PS9 Port n Set Bit 9 9 write-only OUT Port 15 Output Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 Port n Output Bit 0 0 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P1 Port n Output Bit 1 1 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P10 Port n Output Bit 10 10 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P11 Port n Output Bit 11 11 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P12 Port n Output Bit 12 12 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P13 Port n Output Bit 13 13 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P14 Port n Output Bit 14 14 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P15 Port n Output Bit 15 15 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P2 Port n Output Bit 2 2 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P3 Port n Output Bit 3 3 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P4 Port n Output Bit 4 4 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P5 Port n Output Bit 5 5 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P6 Port n Output Bit 6 6 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P7 Port n Output Bit 7 7 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P8 Port n Output Bit 8 8 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P9 Port n Output Bit 9 9 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 PDISC Port 15 Pin Function Decision Control Register 0x60 32 read-write n 0x0 0xFFFF0000 PDIS12 Pad Disable for Port 15 Pin 12 12 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 4. #1 PDIS13 Pad Disable for Port 15 Pin 13 13 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 5. #1 PDIS14 Pad Disable for Port 15 Pin 14 14 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 6. #1 PDIS15 Pad Disable for Port 15 Pin 15 15 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 7. #1 PDIS2 Pad Disable for Port 15 Pin 2 2 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 2. #1 PDIS3 Pad Disable for Port 15 Pin 3 3 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 3. #1 PDIS4 Pad Disable for Port 15 Pin 4 4 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 4. #1 PDIS5 Pad Disable for Port 15 Pin 5 5 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 5. #1 PDIS6 Pad Disable for Port 15 Pin 6 6 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 6. #1 PDIS7 Pad Disable for Port 15 Pin 7 7 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 2 analog input 7. #1 PDIS8 Pad Disable for Port 15 Pin 8 8 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 0. #1 PDIS9 Pad Disable for Port 15 Pin 9 9 read-write value1 Pad is enabled, digital input selected. #0 value2 Pad is disabled, ADC 3 analog input 1. #1 PPS Port 15 Pin Power Save Register 0x70 32 read-write n 0x0 0xFFFFFFFF PPS0 Port n Pin Power Save Bit 0 0 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS1 Port n Pin Power Save Bit 1 1 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS10 Port n Pin Power Save Bit 10 10 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS11 Port n Pin Power Save Bit 11 11 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS12 Port n Pin Power Save Bit 12 12 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS13 Port n Pin Power Save Bit 13 13 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS14 Port n Pin Power Save Bit 14 14 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS15 Port n Pin Power Save Bit 15 15 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS2 Port n Pin Power Save Bit 2 2 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS3 Port n Pin Power Save Bit 3 3 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS4 Port n Pin Power Save Bit 4 4 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS5 Port n Pin Power Save Bit 5 5 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS6 Port n Pin Power Save Bit 6 6 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS7 Port n Pin Power Save Bit 7 7 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS8 Port n Pin Power Save Bit 8 8 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS9 Port n Pin Power Save Bit 9 9 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 GPIO3 General-purpose I/O 3 GPIO 0x41103000 0x0 0x3C registers n GPIO3 GPIO 3 combined 71 ALTFUNCCLR Alternate function clear Register 0x1C read-write n 0x0 0xFFFFFFFF ALTFUNCSET Alternate function set Register 0x18 read-write n 0x0 0xFFFFFFFF DATA Data Register 0x0 read-write n 0x0 0xFFFFFFFF DATAOUT Data Output Register 0x4 read-write n 0x0 0xFFFFFFFF INTCLEAR Interrupt CLEAR Register INTSTATUS 0x38 write-only n 0x0 0xFFFFFFFF oneToClear INTENCLR Interrupt enable clear Register 0x24 read-write n 0x0 0xFFFFFFFF INTENSET Interrupt enable set Register 0x20 read-write n 0x0 0xFFFFFFFF INTPOLCLR Polarity-level, edge interrupt configuration clear Register 0x34 read-write n 0x0 0xFFFFFFFF INTPOLSET Polarity-level, edge interrupt configuration set Register 0x30 read-write n 0x0 0xFFFFFFFF INTSTATUS Interrupt Status Register 0x38 read-only n 0x0 0xFFFFFFFF INTTYPECLR Interrupt type clear Register 0x2C read-write n 0x0 0xFFFFFFFF INTTYPESET Interrupt type set Register 0x28 read-write n 0x0 0xFFFFFFFF OUTENCLR Ouptut enable clear Register 0x14 read-write n 0x0 0xFFFFFFFF OUTENSET Ouptut enable set Register 0x10 read-write n 0x0 0xFFFFFFFF GPIO3_Secure General-purpose I/O 3 (Secure) PPB 0x51103000 0x0 0x1000 registers n ACTLR Auxiliary Control Register 0x8 32 read-write n 0x0 0xFFFFFFFF DISDEFWBUF Disable write buffer 1 read-write DISFOLD Disable IT folding 2 read-write DISFPCA Disable FPCA update 8 read-write DISMCYCINT Disable load/store multiple 0 read-write DISOOFP Disable out of order FP execution 9 read-write AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0xFFFFFFFF VALUE Reserved 0 31 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0xFA050000 0xFFFFFFFF ENDIANNESS Data endianness bit 15 read-only value1 Little-endian #0 value2 Big-endian. #1 PRIGROUP Interrupt priority grouping field 8 2 read-write SYSRESETREQ System reset request 2 write-only value1 no system reset request #0 value2 asserts a signal to the outer system that requests a reset. #1 VECTCLRACTIVE Reserved for Debug use. 1 write-only VECTKEY Register key 16 15 read-write VECTRESET Reserved for Debug use. 0 write-only BFAR BusFault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Address causing the fault 0 31 read-write CCR Configuration and Control Register 0xD14 32 read-write n 0x200 0xFFFFFFFF BFHFNMIGN Bus Fault Hard Fault and NMI Ignore 8 read-write value1 data bus faults caused by load and store instructions cause a lock-up #0 value2 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions. #1 DIV_0_TRP Divide by Zero Trap Enable 4 read-write value1 do not trap divide by 0 #0 value2 trap divide by 0. #1 NONBASETHRDENA Non Base Thread Mode Enable 0 read-write value1 processor can enter Thread mode only when no exception is active. #0 value2 processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. . #1 STKALIGN Stack Alignment 9 read-write value1 4-byte aligned #0 value2 8-byte aligned. #1 UNALIGN_TRP Unaligned Access Trap Enable 3 read-write value1 do not trap unaligned halfword and word accesses #0 value2 trap unaligned halfword and word accesses. #1 USERSETMPEND User Set Pending Enable 1 read-write value1 disable #0 value2 enable #1 CFSR Configurable Fault Status Register 0xD28 32 read-write n 0x0 0xFFFFFFFF BFARVALID BusFault Address Register (BFAR) valid flag 15 read-write value1 value in BFAR is not a valid fault address #0 value2 BFAR holds a valid fault address. #1 DACCVIOL Data access violation flag 1 read-write value1 no data access violation fault #0 value2 the processor attempted a load or store at a location that does not permit the operation. #1 DIVBYZERO Divide by zero UsageFault 25 read-write value1 no divide by zero fault, or divide by zero trapping not enabled #0 value2 the processor has executed an SDIV or UDIV instruction with a divisor of 0 #1 IACCVIOL Instruction access violation flag 0 read-write value1 no instruction access violation fault #0 value2 the processor attempted an instruction fetch from a location that does not permit execution. #1 IBUSERR Instruction bus error 8 read-write value1 no instruction bus error #0 value2 instruction bus error. #1 IMPRECISERR Imprecise data bus error 10 read-write value1 no imprecise data bus error #0 value2 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error. #1 INVPC Invalid PC load UsageFault 18 read-write value1 no invalid PC load UsageFault #0 value2 the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value. #1 INVSTATE Invalid state UsageFault 17 read-write value1 no invalid state UsageFault #0 value2 the processor has attempted to execute an instruction that makes illegal use of the EPSR. #1 LSPERR BusFault during floating point lazy state preservation 13 read-write value1 No bus fault occurred during floating-point lazy state preservation. #0 value2 A bus fault occurred during floating-point lazy state preservation #1 MLSPERR MemManage fault during floating point lazy state preservation 5 read-write value1 No MemManage fault occurred during floating-point lazy state preservation #0 value2 A MemManage fault occurred during floating-point lazy state preservation #1 MMARVALID MemManage Fault Address Register (MMFAR) valid flag 7 read-write value1 value in MMAR is not a valid fault address #0 value2 MMAR holds a valid fault address. #1 MSTKERR MemManage fault on stacking for exception entry 4 read-write value1 no stacking fault #0 value2 stacking for an exception entry has caused one or more access violations. #1 MUNSTKERR MemManage fault on unstacking for a return from exception 3 read-write value1 no unstacking fault #0 value2 unstack for an exception return has caused one or more access violations. #1 NOCP No coprocessor UsageFault 19 read-write value1 no UsageFault caused by attempting to access a coprocessor #0 value2 the processor has attempted to access a coprocessor. #1 PRECISERR Precise data bus error 9 read-write value1 no precise data bus error #0 value2 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault. #1 STKERR BusFault on stacking for exception entry 12 read-write value1 no stacking fault #0 value2 stacking for an exception entry has caused one or more BusFaults. #1 UNALIGNED Unaligned access UsageFault 24 read-write value1 no unaligned access fault, or unaligned access trapping not enabled #0 value2 the processor has made an unaligned memory access. #1 UNDEFINSTR Undefined instruction UsageFault 16 read-write value1 no undefined instruction UsageFault #0 value2 the processor has attempted to execute an undefined instruction. #1 UNSTKERR BusFault on unstacking for a return from exception 11 read-write value1 no unstacking fault #0 value2 stacking for an exception entry has caused one or more BusFaults. #1 CPACR Coprocessor Access Control Register 0xD88 32 read-write n 0x0 0xFFFFFFFF CP10 Access privileges for coprocessor 10 20 1 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault. #00 value2 Privileged access only. An unprivileged access generates a NOCP fault. #01 value4 Full access. #11 CP11 Access privileges for coprocessor 11 22 1 read-write value1 Access denied. Any attempted access generates a NOCP UsageFault. #00 value2 Privileged access only. An unprivileged access generates a NOCP fault. #01 value4 Full access. #11 CPUID CPUID Base Register 0xD00 32 read-write n 0x410FC241 0xFFFFFFFF Constant Reads as 0xF 16 3 read-only Implementer Implementer code 24 7 read-only value1 ARM 0x41 PartNo Part number of the processor 4 11 read-only value1 Cortex-M4 0xC24 Revision Revision number 0 3 read-only value1 Patch 1 0x1 Variant Variant number 20 3 read-only value1 Revision 0 0x0 FPCAR Floating-point Context Address Register 0xF38 32 read-write n 0x0 0xFFFFFFFF ADDRESS Address 3 28 read-write FPCCR Floating-point Context Control Register 0xF34 32 read-write n 0x0 0xFFFFFFFF ASPEN Automatic State Preservation 31 read-write value1 Disable CONTROL setting on execution of a floating-point instruction. #0 value2 Enable CONTROL setting on execution of a floating-point instruction. #1 BFRDY BusFault Ready 6 read-write value1 BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated. #0 value2 BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. #1 HFRDY HardFault Ready 4 read-write value1 Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated. #0 value2 Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. #1 LSPACT Lazy State Preservation Active 0 read-write value1 Lazy state preservation is not active. #0 value2 Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred. #1 LSPEN Lazy State Preservation Enabled 30 read-write value1 Disable automatic lazy state preservation for floating-point context. #0 value2 Enable automatic lazy state preservation for floating-point context. #1 MMRDY MemManage Ready 5 read-write value1 MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated. #0 value2 MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. #1 MONRDY Monitor Ready 8 read-write value1 Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated. #0 value2 Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. #1 THREAD Thread Mode allocated Stack Frame 3 read-write value1 Mode was not Thread Mode when the floating-point stack frame was allocated. #0 value2 Mode was Thread Mode when the floating-point stack frame was allocated. #1 USER User allocated Stack Frame 1 read-write value1 Privilege level was not user when the floating-point stack frame was allocated. #0 value2 Privilege level was user when the floating-point stack frame was allocated. #1 FPDSCR Floating-point Default Status Control Register 0xF3C 32 read-write n 0x0 0xFFFFFFFF AHP Default value for FPSCR.AHP 26 read-write DN Default value for FPSCR.DN 25 read-write FZ Default value for FPSCR.FZ 24 read-write RMode Default value for FPSCR.RMode 22 1 read-write HFSR HardFault Status Register 0xD2C 32 read-write n 0x0 0xFFFFFFFF DEBUGEVT Reserved for Debug use 31 read-write FORCED Forced HardFault 30 read-write value1 no forced HardFault #0 value2 forced HardFault. #1 VECTTBL BusFault on vector table read 1 read-write value1 no BusFault on vector table read #0 value2 BusFault on vector table read #1 ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0xFFFFFFFF ISRPENDING Interrupt pending flag 22 read-only value1 interrupt not pending #0 value2 interrupt pending. #1 NMIPENDSET NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending., 31 read-write PENDSTCLR SysTick exception clear-pending bit 25 write-only value1 no effect #0 value2 removes the pending state from the SysTick exception. #1 PENDSTSET SysTick exception set-pending bit 26 read-write value1 no effect #0 value2 changes SysTick exception state to pending. #1 PENDSVCLR PendSV clear-pending bit 27 write-only value1 no effect #0 value2 removes the pending state from the PendSV exception. #1 PENDSVSET PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending., 28 read-write RETTOBASE Return to Base 11 read-only value1 there are preempted active exceptions to execute #0 value2 there are no active exceptions, or the currently-executing exception is the only active exception. #1 VECTACTIVE Active exception number 0 8 read-only value1 Thread mode 0x00 VECTPENDING Vector Pending 12 5 read-only value1 no pending exceptions 0x0 MMFAR MemManage Fault Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Address causing the fault 0 31 read-write MPU_CTRL MPU Control Register 0xD94 32 read-write n 0x0 0xFFFFFFFF ENABLE Enable MPU 0 read-write value1 MPU disabled #0 value2 MPU enabled. #1 HFNMIENA Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers 1 read-write value1 MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit #0 value2 the MPU is enabled during hard fault, NMI, and FAULTMASK handlers. #1 PRIVDEFENA Enables privileged software access to the default memory map 2 read-write value1 If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault. #0 value2 If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses. #1 MPU_RASR MPU Region Attribute and Size Register 0xDA0 32 read-write n 0x0 0xFFFFFFFF AP Access permission field 24 2 read-write B Memory access attribute 16 read-write C Memory access attribute 17 read-write ENABLE Region enable bit. 0 read-write S Shareable bit 18 read-write SIZE MPU protection region size 1 4 read-write SRD Subregion disable bits 8 7 read-write value1 corresponding sub-region is enabled #0 value2 corresponding sub-region is disabled #1 TEX Memory access attribute 19 2 read-write XN Instruction access disable bit 28 read-write value1 instruction fetches enabled #0 value2 instruction fetches disabled. #1 MPU_RASR_A1 MPU Region Attribute and Size Register A1 0xDA8 32 read-write n 0x0 0xFFFFFFFF AP Access permission field 24 2 read-write B Memory access attribute 16 read-write C Memory access attribute 17 read-write ENABLE Region enable bit. 0 read-write S Shareable bit 18 read-write SIZE MPU protection region size 1 4 read-write SRD Subregion disable bits 8 7 read-write value1 corresponding sub-region is enabled #0 value2 corresponding sub-region is disabled #1 TEX Memory access attribute 19 2 read-write XN Instruction access disable bit 28 read-write value1 instruction fetches enabled #0 value2 instruction fetches disabled. #1 MPU_RASR_A2 MPU Region Attribute and Size Register A2 0xDB0 32 read-write n 0x0 0xFFFFFFFF AP Access permission field 24 2 read-write B Memory access attribute 16 read-write C Memory access attribute 17 read-write ENABLE Region enable bit. 0 read-write S Shareable bit 18 read-write SIZE MPU protection region size 1 4 read-write SRD Subregion disable bits 8 7 read-write value1 corresponding sub-region is enabled #0 value2 corresponding sub-region is disabled #1 TEX Memory access attribute 19 2 read-write XN Instruction access disable bit 28 read-write value1 instruction fetches enabled #0 value2 instruction fetches disabled. #1 MPU_RASR_A3 MPU Region Attribute and Size Register A3 0xDB8 32 read-write n 0x0 0xFFFFFFFF AP Access permission field 24 2 read-write B Memory access attribute 16 read-write C Memory access attribute 17 read-write ENABLE Region enable bit. 0 read-write S Shareable bit 18 read-write SIZE MPU protection region size 1 4 read-write SRD Subregion disable bits 8 7 read-write value1 corresponding sub-region is enabled #0 value2 corresponding sub-region is disabled #1 TEX Memory access attribute 19 2 read-write XN Instruction access disable bit 28 read-write value1 instruction fetches enabled #0 value2 instruction fetches disabled. #1 MPU_RBAR MPU Region Base Address Register 0xD9C 32 read-write n 0x0 0xFFFFFFFF ADDR Region base address field 9 22 read-write REGION MPU region field 0 3 read-write VALID MPU Region Number valid bit 4 read-write value1 MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field #0 value2 the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. #1 MPU_RBAR_A1 MPU Region Base Address Register A1 0xDA4 32 read-write n 0x0 0xFFFFFFFF ADDR Region base address field 9 22 read-write REGION MPU region field 0 3 read-write VALID MPU Region Number valid bit 4 read-write value1 MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field #0 value2 the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. #1 MPU_RBAR_A2 MPU Region Base Address Register A2 0xDAC 32 read-write n 0x0 0xFFFFFFFF ADDR Region base address field 9 22 read-write REGION MPU region field 0 3 read-write VALID MPU Region Number valid bit 4 read-write value1 MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field #0 value2 the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. #1 MPU_RBAR_A3 MPU Region Base Address Register A3 0xDB4 32 read-write n 0x0 0xFFFFFFFF ADDR Region base address field 9 22 read-write REGION MPU region field 0 3 read-write VALID MPU Region Number valid bit 4 read-write value1 MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field #0 value2 the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field. #1 MPU_RNR MPU Region Number Register 0xD98 32 read-write n 0x0 0xFFFFFFFF REGION Region 0 7 read-write MPU_TYPE MPU Type Register 0xD90 32 read-write n 0x800 0xFFFFFFFF DREGION Number of supported MPU data regions 8 7 read-only IREGION Number of supported MPU instruction regions 16 7 read-only SEPARATE Support for unified or separate instruction and date memory maps 0 read-only NVIC_IABR0 Interrupt Active Bit Register 0 0x300 32 read-write n 0x0 0xFFFFFFFF ACTIVE Interrupt active flags: 0 31 read-write value1 interrupt not active #0 value2 interrupt active #1 NVIC_IABR1 Interrupt Active Bit Register 1 0x304 32 read-write n 0x0 0xFFFFFFFF ACTIVE Interrupt active flags: 0 31 read-write value1 interrupt not active #0 value2 interrupt active #1 NVIC_IABR2 Interrupt Active Bit Register 2 0x308 32 read-write n 0x0 0xFFFFFFFF ACTIVE Interrupt active flags: 0 31 read-write value1 interrupt not active #0 value2 interrupt active #1 NVIC_IABR3 Interrupt Active Bit Register 3 0x30C 32 read-write n 0x0 0xFFFFFFFF ACTIVE Interrupt active flags: 0 31 read-write value1 interrupt not active #0 value2 interrupt active #1 NVIC_ICER0 Interrupt Clear-enable Register 0 0x180 32 read-write n 0x0 0xFFFFFFFF CLRENA Interrupt clear-enable bits. 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ICER1 Interrupt Clear-enable Register 1 0x184 32 read-write n 0x0 0xFFFFFFFF CLRENA Interrupt clear-enable bits. 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ICER2 Interrupt Clear-enable Register 2 0x188 32 read-write n 0x0 0xFFFFFFFF CLRENA Interrupt clear-enable bits. 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ICER3 Interrupt Clear-enable Register 3 0x18C 32 read-write n 0x0 0xFFFFFFFF CLRENA Interrupt clear-enable bits. 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ICPR0 Interrupt Clear-pending Register 0 0x280 32 read-write n 0x0 0xFFFFFFFF CLRPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ICPR1 Interrupt Clear-pending Register 1 0x284 32 read-write n 0x0 0xFFFFFFFF CLRPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ICPR2 Interrupt Clear-pending Register 2 0x288 32 read-write n 0x0 0xFFFFFFFF CLRPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ICPR3 Interrupt Clear-pending Register 3 0x28C 32 read-write n 0x0 0xFFFFFFFF CLRPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_IPR0 Interrupt Priority Register 0 0x400 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR1 Interrupt Priority Register 1 0x404 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR10 Interrupt Priority Register 10 0x428 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR11 Interrupt Priority Register 11 0x42C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR12 Interrupt Priority Register 12 0x430 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR13 Interrupt Priority Register 13 0x434 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR14 Interrupt Priority Register 14 0x438 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR15 Interrupt Priority Register 15 0x43C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR16 Interrupt Priority Register 16 0x440 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR17 Interrupt Priority Register 17 0x444 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR18 Interrupt Priority Register 18 0x448 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR19 Interrupt Priority Register 19 0x44C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR2 Interrupt Priority Register 2 0x408 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR20 Interrupt Priority Register 20 0x450 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR21 Interrupt Priority Register 21 0x454 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR22 Interrupt Priority Register 22 0x458 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR23 Interrupt Priority Register 23 0x45C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR24 Interrupt Priority Register 24 0x460 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR25 Interrupt Priority Register 25 0x464 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR26 Interrupt Priority Register 26 0x468 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR27 Interrupt Priority Register 27 0x46C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR3 Interrupt Priority Register 3 0x40C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR4 Interrupt Priority Register 4 0x410 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR5 Interrupt Priority Register 5 0x414 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR6 Interrupt Priority Register 6 0x418 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR7 Interrupt Priority Register 7 0x41C 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR8 Interrupt Priority Register 8 0x420 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_IPR9 Interrupt Priority Register 9 0x424 32 read-write n 0x0 0xFFFFFFFF PRI_0 Priority value 0 0 7 read-write PRI_1 Priority value 1 8 7 read-write PRI_2 Priority value 2 16 7 read-write PRI_3 Priority value 3 24 7 read-write NVIC_ISER0 Interrupt Set-enable Register 0 0x100 32 read-write n 0x0 0xFFFFFFFF SETENA Interrupt set-enable bits 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ISER1 Interrupt Set-enable Register 1 0x104 32 read-write n 0x0 0xFFFFFFFF SETENA Interrupt set-enable bits 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ISER2 Interrupt Set-enable Register 2 0x108 32 read-write n 0x0 0xFFFFFFFF SETENA Interrupt set-enable bits 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ISER3 Interrupt Set-enable Register 3 0x10C 32 read-write n 0x0 0xFFFFFFFF SETENA Interrupt set-enable bits 0 31 read-write value3 interrupt disabled #0 value4 interrupt enabled. #1 NVIC_ISPR0 Interrupt Set-pending Register 0 0x200 32 read-write n 0x0 0xFFFFFFFF SETPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ISPR1 Interrupt Set-pending Register 1 0x204 32 read-write n 0x0 0xFFFFFFFF SETPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ISPR2 Interrupt Set-pending Register 2 0x208 32 read-write n 0x0 0xFFFFFFFF SETPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 NVIC_ISPR3 Interrupt Set-pending Register 3 0x20C 32 read-write n 0x0 0xFFFFFFFF SETPEND Interrupt set-pending bits. 0 31 read-write value3 interrupt is not pending #0 value4 interrupt is pending. #1 SCR System Control Register 0xD10 32 read-write n 0x0 0xFFFFFFFF SEVONPEND Send Event on Pending bit: 4 read-write value1 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 value2 enabled events and all interrupts, including disabled interrupts, can wakeup the processor. #1 SLEEPDEEP Sleep or Deep Sleep 2 read-write value1 sleep #0 value2 deep sleep #1 SLEEPONEXIT Sleep on Exit 1 read-write value1 do not sleep when returning to Thread mode. #0 value2 enter sleep, or deep sleep, on return from an ISR. #1 SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0xFFFFFFFF BUSFAULTACT BusFault exception active bit 1 read-write BUSFAULTENA BusFault enable bit 17 read-write BUSFAULTPENDED BusFault exception pending bit 14 read-write MEMFAULTACT MemManage exception active bit 0 read-write MEMFAULTENA MemManage enable bit 16 read-write MEMFAULTPENDED MemManage exception pending bit 13 read-write MONITORACT Debug monitor active bit 8 read-write PENDSVACT PendSV exception active bit 10 read-write SVCALLACT SVCall active bit 7 read-write SVCALLPENDED SVCall pending bit 15 read-write SYSTICKACT SysTick exception active bit 11 read-write USGFAULTACT UsageFault exception active bit 3 read-write USGFAULTENA UsageFault enable bit 18 read-write USGFAULTPENDED UsageFault exception pending bit 12 read-write SHPR1 System Handler Priority Register 1 0xD18 32 read-write n 0x0 0xFFFFFFFF PRI_4 Priority of system handler 4, MemManage 0 7 read-write PRI_5 Priority of system handler 5, BusFault 8 7 read-write PRI_6 Priority of system handler 6, UsageFault 16 7 read-write SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0xFFFFFFFF PRI_11 Priority of system handler 11, SVCall 24 7 read-write SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0xFFFFFFFF PRI_14 Priority of system handler 14 16 7 read-write PRI_15 Priority of system handler 15 24 7 read-write STIR Software Trigger Interrupt Register 0xF00 32 read-write n 0x0 0xFFFFFFFF INTID Interrupt ID of the interrupt to trigger 0 8 write-only SYST_CALIB SysTick Calibration Value Register r 0x1C 32 read-write n 0xC0000000 0xFFFFFFFF NOREF No Reference Clock 31 read-write value1 reference clock provided #0 value2 no reference clock provided. #1 SKEW Ten Milliseconds Skewed 30 read-write value1 TENMS value is exact #0 value2 TENMS value is inexact, or not given. #1 TENMS Ten Milliseconds Reload Value 0 23 read-write SYST_CSR SysTick Control and Status Register 0x10 32 read-write n 0x4 0xFFFFFFFF CLKSOURCE Indicates the clock source: 2 read-write value1 external clock #0 value2 processor clock. #1 COUNTFLAG Counter Flag 16 read-write ENABLE Enable 0 read-write value1 counter disabled #0 value2 counter enabled. #1 TICKINT Tick Interrupt Enable 1 read-write value1 counting down to zero does not assert the SysTick exception request #0 value2 counting down to zero to asserts the SysTick exception request. #1 SYST_CVR SysTick Current Value Register 0x18 32 read-write n 0x0 0x0 CURRENT Current Value 0 23 read-write SYST_RVR SysTick Reload Value Register 0x14 32 read-write n 0x0 0x0 RELOAD Reload Value 0 23 read-write VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0xFFFFFFFF TBLOFF Vector table base offset field 10 21 read-write I2C0 I2C 0 I2C 0x41200000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C0_Secure I2C 0 (Secure) I2C 0x51200000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C1 I2C 1 I2C 0x41201000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C1_Secure I2C 1 (Secure) PBA 0x51201000 0x0 0x50 registers n STS Peripheral Bridge Status Register 0x0 32 read-write n 0x0 0xFFFFFFFF WERR Bufferable Write Access Error 0 read-write value1 no write error occurred. #0 value2 write error occurred, interrupt request is pending. #1 WADDR PBA Write Error Address Register 0x4 32 read-write n 0x0 0xFFFFFFFF WADDR Write Error Address 0 31 read-only I2C2 I2C 2 I2C 0x41205000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C2_Secure I2C 2 (Secure) FLASH0 0x51205000 0x0 0x1400 registers n FCON Flash Configuration Register 0x1014 32 read-write n 0x0 0xFFF0FFFF DCF Disable Code Fetch from Flash Memory 17 read-write value1 Code fetching from the Flash memory area is allowed. #0 value2 Code fetching from the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. #1 DDF Disable Any Data Fetch from Flash 18 read-write value1 Data read access to the Flash memory area is allowed. #0 value2 Data read access to the Flash memory area is not allowed. This bit is not taken into account while RPA='0'. #1 EOBM End of Busy Interrupt Mask 31 read-write value1 Interrupt not enabled #0 value2 EOB interrupt is enabled #1 ESLDIS External Sleep Request Disable 14 read-write value1 External sleep request signal input is enabled #0 value2 Externally requested Flash sleep is disabled #1 IDLE Dynamic Flash Idle 13 read-write value1 Normal/standard Flash read operation #0 value2 Dynamic idle of Program Flash enabled for power saving; static prefetching disabled #1 PFDBERM PFLASH Double-Bit Error Interrupt Mask 29 read-write value1 Double-Bit Error interrupt for PFLASH not enabled #0 value2 Double-Bit Error interrupt for PFLASH enabled. Especially intended for margin check #1 PFSBERM PFLASH Single-Bit Error Interrupt Mask 27 read-write value1 No Single-Bit Error interrupt enabled #0 value2 Single-Bit Error interrupt enabled for PFLASH #1 PROERM Protection Error Interrupt Mask 26 read-write value1 Interrupt not enabled #0 value2 Flash interrupt because of Protection Error is enabled #1 RPA Read Protection Activated 16 read-only value1 The Flash-internal read protection is not activated. Bits DCF, DDF are not taken into account. Bits DCF, DDFx can be cleared #0 value2 The Flash-internal read protection is activated. Bits DCF, DDF are enabled and evaluated. #1 SLEEP Flash SLEEP 15 read-write value1 Normal state or wake-up #0 value2 Flash sleep mode is requested #1 SQERM Command Sequence Error Interrupt Mask 25 read-write value1 Interrupt not enabled #0 value2 Flash interrupt because of Sequence Error is enabled #1 VOPERM Verify and Operation Error Interrupt Mask 24 read-write value1 Interrupt not enabled #0 value2 Flash interrupt because of Verify Error or Operation Error in Flash array (FSI) is enabled #1 WSECPF Wait State for Error Correction of PFLASH 4 read-write value1 No additional wait state for error correction #0 value2 One additional wait state for error correction during read access to Program Flash. If enabled, this wait state is only used for the first transfer of a burst transfer. #1 WSPFLASH Wait States for read access to PFLASH 0 3 read-write value1 PFLASH access in one clock cycle #0000 value2 PFLASH access in one clock cycle #0001 value3 PFLASH access in two clock cycles #0010 value4 PFLASH access in three clock cycles #0011 value5 PFLASH access in fifteen clock cycles. #1111 FSR Flash Status Register 0x1010 32 read-write n 0x0 0xFFFFFFFF ERASE Erase State 5 read-only value1 There is no erase operation requested or in progress or just finished #0 value2 Erase operation requested (from FIM) or in action or finished. #1 FABUSY Flash Array Busy 1 read-only PBUSY Program Flash Busy 0 read-only value1 PFLASH ready, not busy; PFLASH in read mode. #0 value2 PFLASH busy; PFLASH not in read mode. #1 PFDBER PFLASH Double-Bit Error 14 read-only value1 No Double-Bit Error detected during read access to PFLASH #0 value2 Double-Bit Error detected in PFLASH #1 PFOPER Program Flash Operation Error 8 read-only value1 No operation error reported by Program Flash #0 value2 Flash array operation aborted, because of a Flash array failure, e.g. an ECC error in microcode. #1 PFPAGE Program Flash in Page Mode 6 read-only value1 Program Flash not in page mode #0 value2 Program Flash in page mode; assembly buffer of PFLASH (256 byte) is in use (being filled up) #1 PFSBER PFLASH Single-Bit Error and Correction 12 read-only value1 No Single-Bit Error detected during read access to PFLASH #0 value2 Single-Bit Error detected and corrected #1 PROER Protection Error 11 read-only value1 No protection error #0 value2 Protection error. #1 PROG Programming State 4 read-only value1 There is no program operation requested or in progress or just finished. #0 value2 Programming operation (write page) requested (from FIM) or in action or finished. #1 PROIN Protection Installed 16 read-only value1 No protection is installed #0 value2 Read or/and write protection for one or more users is configured and correctly confirmed in the User Configuration Block(s). #1 RPRODIS Read Protection Disable State 19 read-only value1 Read protection (if installed) is not disabled #0 value2 Read and global write protection is temporarily disabled. #1 RPROIN Read Protection Installed 18 read-only value1 No read protection installed #0 value2 Read protection and global write protection is configured and correctly confirmed in the User Configuration Block 0. #1 SLM Flash Sleep Mode 28 read-only value1 Flash not in sleep mode #0 value2 Flash is in sleep or shut down mode #1 SQER Command Sequence Error 10 read-only value1 No sequence error #0 value2 Command state machine operation unsuccessful because of improper address or command sequence. #1 VER Verify Error 31 read-only value1 The page is correctly programmed or the sector correctly erased. All programmed or erased bits have full expected quality. #0 value2 A program verify error or an erase verify error has been detected. Full quality (retention time) of all programmed ("1") or erased ("0") bits cannot be guaranteed. #1 WPRODIS0 Sector Write Protection Disabled for User 0 25 read-only value1 All protected sectors of user 0 are locked if write protection is installed #0 value2 All write-protected sectors of user 0 are temporarily unlocked, if not coincidently locked by user 2 or via read protection. #1 WPRODIS1 Sector Write Protection Disabled for User 1 26 read-only value1 All protected sectors of user 1 are locked if write protection is installed #0 value2 All write-protected sectors of user 1 are temporarily unlocked, if not coincidently locked by user 0 or user 2 or via read protection. #1 WPROIN0 Sector Write Protection Installed for User 0 21 read-only value1 No write protection installed for user 0 #0 value2 Sector write protection for user 0 is configured and correctly confirmed in the User Configuration Block 0. #1 WPROIN1 Sector Write Protection Installed for User 1 22 read-only value1 No write protection installed for user 1 #0 value2 Sector write protection for user 1 is configured and correctly confirmed in the User Configuration Block 1. #1 WPROIN2 Sector OTP Protection Installed for User 2 23 read-only value1 No OTP write protection installed for user 2 #0 value2 Sector OTP write protection with ROM functionality is configured and correctly confirmed in the UCB2. The protection is locked for ever. #1 ID Flash Module Identification Register 0x1008 32 read-write n 0x0 0xFFFFFF00 MOD_NUMBER Module Number Value 16 15 read-only MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 7 read-only MARP Margin Control Register PFLASH 0x1018 32 read-write n 0x0 0xFFFFFFFF MARGIN PFLASH Margin Selection 0 3 read-write value1 Standard (default) margin. #0000 value2 Tight margin for 0 (low) level. Suboptimal 0-bits are read as 1s. #0001 value3 Tight margin for 1 (high) level. Suboptimal 1-bits are read as 0s. #0100 TRAPDIS PFLASH Double-Bit Error Trap Disable 15 read-write value1 If a double-bit error occurs in PFLASH, a bus error trap is generated. #0 value2 The double-bit error trap is disabled. Shall be used only during margin check #1 PROCON0 Flash Protection Configuration Register User 0 0x1020 32 read-write n 0x0 0xFFFF0000 RPRO Read Protection Configuration 15 read-only value1 No read protection configured #0 value2 Read protection and global write protection is configured by user 0 (master user) #1 S0L Sector 0 Locked for Write Protection by User 0 0 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S10_S11L Sectors 10 and 11 Locked for Write Protection by User 0 10 read-only value1 No write protection is configured for sectors 10+11. #0 value2 Write protection is configured for sectors 10+11. #1 S12_S13L Sectors 12 and 13 Locked for Write Protection by User 0 11 read-only value1 No write protection is configured for sectors 12+13. #0 value2 Write protection is configured for sectors 12+13. #1 S14_S15L Sectors 14 and 15 Locked for Write Protection by User 0 12 read-only value1 No write protection is configured for sectors 14+15. #0 value2 Write protection is configured for sectors 14+15. #1 S1L Sector 1 Locked for Write Protection by User 0 1 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S2L Sector 2 Locked for Write Protection by User 0 2 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S3L Sector 3 Locked for Write Protection by User 0 3 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S4L Sector 4 Locked for Write Protection by User 0 4 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S5L Sector 5 Locked for Write Protection by User 0 5 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S6L Sector 6 Locked for Write Protection by User 0 6 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S7L Sector 7 Locked for Write Protection by User 0 7 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S8L Sector 8 Locked for Write Protection by User 0 8 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S9L Sector 9 Locked for Write Protection by User 0 9 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 PROCON1 Flash Protection Configuration Register User 1 0x1024 32 read-write n 0x0 0xFFFF0000 PSR Physical Sector Repair 16 read-only value1 Physical Sector Repair command disabled; Erase Physical Sector command sequence available. #0 value2 Physical Sector Repair command sequence enabled; Erase Physical Sector command sequence disabled. #1 S0L Sector 0 Locked for Write Protection by User 1 0 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S10_S11L Sectors 10 and 11 Locked for Write Protection by User 1 10 read-only value1 No write protection is configured for sectors 10+11. #0 value2 Write protection is configured for sectors 10+11. #1 S12_S13L Sectors 12 and 13 Locked for Write Protection by User 1 11 read-only value1 No write protection is configured for sectors 12+13. #0 value2 Write protection is configured for sectors 12+13. #1 S14_S15L Sectors 14 and 15 Locked for Write Protection by User 1 12 read-only value1 No write protection is configured for sectors 14+15. #0 value2 Write protection is configured for sectors 14+15. #1 S1L Sector 1 Locked for Write Protection by User 1 1 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S2L Sector 2 Locked for Write Protection by User 1 2 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S3L Sector 3 Locked for Write Protection by User 1 3 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S4L Sector 4 Locked for Write Protection by User 1 4 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S5L Sector 5 Locked for Write Protection by User 1 5 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S6L Sector 6 Locked for Write Protection by User 1 6 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S7L Sector 7 Locked for Write Protection by User 1 7 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S8L Sector 8 Locked for Write Protection by User 1 8 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 S9L Sector 9 Locked for Write Protection by User 1 9 read-only value1 No write protection is configured for sector n. #0 value2 Write protection is configured for sector n. #1 PROCON2 Flash Protection Configuration Register User 2 0x1028 32 read-write n 0x0 0xFFFF0000 S0ROM Sector 0 Locked Forever by User 2 0 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S10_S11ROM Sectors 10 and 11 Locked Forever by User 2 10 read-only value1 No ROM functionality is configured for sectors 10+11. #0 value2 ROM functionality is configured for sectors 10+11. #1 S12_S13ROM Sectors 12 and 13 Locked Forever by User 2 11 read-only value1 No ROM functionality is configured for sectors 12+13. #0 value2 ROM functionality is configured for sectors 12+13. #1 S14_S15ROM Sectors 14 and 15 Locked Forever by User 2 12 read-only value1 No ROM functionality is configured for sectors 14+15. #0 value2 ROM functionality is configured for sectors 14+15. #1 S1ROM Sector 1 Locked Forever by User 2 1 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S2ROM Sector 2 Locked Forever by User 2 2 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S3ROM Sector 3 Locked Forever by User 2 3 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S4ROM Sector 4 Locked Forever by User 2 4 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S5ROM Sector 5 Locked Forever by User 2 5 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S6ROM Sector 6 Locked Forever by User 2 6 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S7ROM Sector 7 Locked Forever by User 2 7 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S8ROM Sector 8 Locked Forever by User 2 8 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 S9ROM Sector 9 Locked Forever by User 2 9 read-only value1 No ROM functionality configured for sector n. #0 value2 ROM functionality is configured for sector n. Re-programming of this sector is no longer possible. #1 I2C3 I2C 3 I2C 0x41206000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C3_Secure I2C 3 (Secure) PREF 0x51206000 0x0 0x4 registers n PCON Prefetch Configuration Register 0x0 32 read-write n 0x0 0xFFFFFFFF DBYP Data Buffer Bypass 4 read-write value1 Prefetch Data buffer not bypassed. #0 value2 Prefetch Data buffer bypassed. #1 IBYP Instruction Prefetch Buffer Bypass 0 read-write value1 Instruction prefetch buffer not bypassed. #0 value2 Instruction prefetch buffer bypassed. #1 IINV Instruction Prefetch Buffer Invalidate 1 write-only value1 No effect. #0 value2 Initiate invalidation of entire instruction cache. #1 I2C4 I2C 4 I2C 0x41208000 0x0 0xC registers n CONTROL Control Status CONTROLS 0x0 read-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLC Control Clear 0x4 read-write n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 CONTROLS Control Set 0x0 write-only n 0x0 0xFFFFFFFF SCL Serial clock line 0 1 SDA Serial data line 1 2 I2C4_Secure I2C 4 (Secure) PMU0 0x51208000 0x0 0x4 registers n ID PMU0 Identification Register 0x0 32 read-write n 0x0 0xFFFFFF00 MOD_NUMBER Module Number Value 16 15 read-only MOD_REV Module Revision Number 0 7 read-only MOD_TYPE Module Type 8 7 read-only NSPCTRL Non-secure Privilege Control Block NSPCTRL 0x40080000 0x0 0x1000 registers n AHBNSPPPC0 Non-Secure Unprivileged Access AHB slave Peripheral Protection Control #0 0x90 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC0 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPC1 Non-Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP0 Expansion 0 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP1 Expansion 1 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP2 Expansion 2 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBNSPPPCEXP3 Expansion 3 Non_Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x53 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x0 0xFFFFFFFF S32KTIMER S32K Timer Timer 0x4002F000 0x0 0x10 registers n S32KTIMER Timer 1 2 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF S32KWATCHDOG_Secure S32K Watchdog (Secure) WATCHDOG 0x5002E000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF SAU Security Attribution Unit SAU 0xE000EDD0 0x0 0x20 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ALLNS Security attribution if SAU disabled 1 2 Secure Memory is marked as secure 0 Non_Secure Memory is marked as non-secure 1 ENABLE Enable 0 1 Disable SAU is disabled 0 Enable SAU is enabled 1 RBAR Region Base Address Register 0xC read-write n 0x0 0xFFFFFFFF BADDR Base Address 5 32 RLAR Region Limit Address Register 0x10 read-write n 0x0 0xFFFFFFFF ENABLE SAU Region enabled 0 1 LADDR Limit Address 5 32 NSC Non-Secure Callable 1 2 RNR Region Number Register 0x8 read-write n 0x0 0xFFFFFFFF REGION Currently selected SAU region 0 8 SAU_Region_0 Select SAU Region 0 0 SAU_Region_1 Select SAU Region 1 1 SAU_Region_2 Select SAU Region 2 2 SAU_Region_3 Select SAU Region 3 3 SFSR Secure Fault Status Register 0x14 read-write n 0x0 0xFFFFFFFF AUVIOL Attribution unit violation flag 3 4 INVEP Invalid entry pointd 0 1 INVER Invalid exception return flag 2 3 INVIS Invalid integrity signature flag 1 2 INVTRAN Invalid transition flag 4 5 LSERR Lazy state error flag 7 8 LSPERR Lazy state preservation error flag 5 6 SFARVALID Secure fault address valid 6 7 TYPE Type Register 0x4 read-only n 0x0 0xFFFFFFFF SREGION Number of implemented SAU regions 0 8 SCC Serial Communication Controller SCC 0x41300000 0x0 0x1000 registers n AID 0xFF8 32 read-only n 0x0 0xFFFFFFFF FPGA_BUILD FPGA Build Number 24 32 MPS3_REV V2M-MPS3 target Board Revision (A=0,B=1,C=2) 20 24 NUM_CFG_REG Number of SCC configuration register 0 8 CFG_REG0 0x0 32 read-write n 0x0 0xFFFFFFFF REMAP 1 = REMAP Block RAM to ZBT 0 1 CFG_REG1 0x4 32 read-write n 0x0 0xFFFFFFFF CFG_REG2 0x8 32 read-only n 0x0 0xFFFFFFFF QSPI_Select_signal 0 1 Disabled Select signal is off 0 Enabled Select signal is on 1 CFG_REG3 RESERVED 0xC 32 read-only n 0x0 0xFFFFFFFF CFG_REG4 0x10 32 read-only n 0x0 0xFFFFFFFF BRDREV Board Revision 0 4 CFG_REG5 ACLK Frequency in HZ 0x14 32 read-write n 0x0 0xFFFFFFFF ID 0xFFC 32 read-only n 0x0 0xFFFFFFFF APP_NOTE_VAR Application note IP variant number 20 24 APP_REV Application note IP revision number 0 4 IMPLEMENTER_ID Implementer ID: 0x41 = ARM 24 32 IP_ARCH IP Architecture: 0x4 = AHB 16 20 PRI_NUM Primary Part Number: 524 = AN524 4 12 SYS_CFGDATA_OUT 0xA4 32 read-write n 0x0 0xFFFFFFFF SYS_CFGDATA_RTN 0xA0 32 read-write n 0x0 0xFFFFFFFF SCC_Secure Serial Communication Controller SCC 0x51300000 0x0 0x1000 registers n AID 0xFF8 32 read-only n 0x0 0xFFFFFFFF FPGA_BUILD FPGA Build Number 24 32 MPS3_REV V2M-MPS3 target Board Revision (A=0,B=1,C=2) 20 24 NUM_CFG_REG Number of SCC configuration register 0 8 CFG_REG0 0x0 32 read-write n 0x0 0xFFFFFFFF REMAP 1 = REMAP Block RAM to ZBT 0 1 CFG_REG1 0x4 32 read-write n 0x0 0xFFFFFFFF CFG_REG2 0x8 32 read-only n 0x0 0xFFFFFFFF QSPI_Select_signal 0 1 Disabled Select signal is off 0 Enabled Select signal is on 1 CFG_REG3 RESERVED 0xC 32 read-only n 0x0 0xFFFFFFFF CFG_REG4 0x10 32 read-only n 0x0 0xFFFFFFFF BRDREV Board Revision 0 4 CFG_REG5 ACLK Frequency in HZ 0x14 32 read-write n 0x0 0xFFFFFFFF ID 0xFFC 32 read-only n 0x0 0xFFFFFFFF APP_NOTE_VAR Application note IP variant number 20 24 APP_REV Application note IP revision number 0 4 IMPLEMENTER_ID Implementer ID: 0x41 = ARM 24 32 IP_ARCH IP Architecture: 0x4 = AHB 16 20 PRI_NUM Primary Part Number: 524 = AN524 4 12 SYS_CFGDATA_OUT 0xA4 32 read-write n 0x0 0xFFFFFFFF SYS_CFGDATA_RTN 0xA0 32 read-write n 0x0 0xFFFFFFFF SPCTRL Secure Privilege Control Block SPCTRL 0x50080000 0x0 0x1000 registers n AHBNSPPC0 Non-Secure Access AHB slave Peripheral Protection Control 0 0x50 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP0 Expansion 0 Non_Secure Access AHB slave Peripheral Protection Control 0x60 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP1 Expansion 1 Non_Secure Access AHB slave Peripheral Protection Control 0x64 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP2 Expansion 2 Non_Secure Access AHB slave Peripheral Protection Control 0x68 32 read-write n 0x0 0xFFFFFFFF AHBNSPPCEXP3 Expansion 3 Non_Secure Access AHB slave Peripheral Protection Control 0x6C 32 read-write n 0x0 0xFFFFFFFF AHBSPPPC0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0 0x90 32 read-only n 0x0 0xFFFFFFFF AHBSPPPCEXP0 Expansion 0 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA0 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP1 Expansion 1 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA4 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP2 Expansion 2 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xA8 32 read-write n 0x0 0xFFFFFFFF AHBSPPPCEXP3 Expansion 3 Secure Unprivileged Access AHB slave Peripheral Protection Control 0xAC 32 read-write n 0x0 0xFFFFFFFF APBNSPPC0 Non-Secure Access APB slave Peripheral Protection Control 0 0x70 32 read-write n 0x0 0xFFFFFFFF APBNSPPC1 Non-Secure Access APB slave Peripheral Protection Control 1 0x74 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP0 Expansion 0 Non_Secure Access APB slave Peripheral Protection Control 0x80 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP1 Expansion 1 Non_Secure Access APB slave Peripheral Protection Control 0x84 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP2 Expansion 2 Non_Secure Access APB slave Peripheral Protection Control 0x88 32 read-write n 0x0 0xFFFFFFFF APBNSPPCEXP3 Expansion 3 Non_Secure Access APB slave Peripheral Protection Control 0x8C 32 read-write n 0x0 0xFFFFFFFF APBSPPPC0 Secure Unprivileged Access APB slave Peripheral Protection Control 0 0xB0 32 read-write n 0x0 0xFFFFFFFF APBSPPPC1 Secure Unprivileged Access APB slave Peripheral Protection Control 1 0xB4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP0 Expansion 0 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC0 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP1 Expansion 1 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC4 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP2 Expansion 2 Secure Unprivileged Access APB slave Peripheral Protection Control 0xC8 32 read-write n 0x0 0xFFFFFFFF APBSPPPCEXP3 Expansion 3 Secure Unprivileged Access APB slave Peripheral Protection Control 0xCC 32 read-write n 0x0 0xFFFFFFFF BRGINTCLR Bridge Buffer Error Interrupt Clear 0x44 32 write-only n 0x0 0xFFFFFFFF BRGINTEN Bridge Buffer Error Interrupt Enable 0x48 32 read-write n 0x0 0xFFFFFFFF BRGINTSTAT Bridge Buffer Error Interrupt Status 0x40 32 read-only n 0x0 0xFFFFFFFF BUSWAIT Bus Access wait control after reset 0x4 32 read-write n 0x0 0xFFFFFFFF CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF NSCCFG Non Secure Callable Configuration for IDAU 0x14 32 read-write n 0x0 0xFFFFFFFF NSMSCEXP Expansion MSC Non-Secure Configuration 0xD0 32 read-only n 0x0 0xFFFFFFFF PID0 Peripheral ID 0 0xFE0 32 read-only n 0x52 0xFFFFFFFF PID1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PID2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF PID3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF PID4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF SECMPCINTSTATUS Secure MPC Interrupt Status 0x1C 32 read-only n 0x0 0xFFFFFFFF SECMSCINTCLR Secure MSC Interrupt Clear 0x34 32 read-write n 0x0 0xFFFFFFFF SECMSCINTEN Secure MSC Interrupt Enable 0x38 32 read-write n 0x0 0xFFFFFFFF SECMSCINTSTAT Secure MSC Interrupt Status 0x30 32 read-only n 0x0 0xFFFFFFFF SECPPCINTCLR Secure PPC Interrupt Clear 0x24 32 write-only n 0x0 0xFFFFFFFF SECPPCINTEN Secure PPC Interrupt Enable 0x28 32 read-write n 0x0 0xFFFFFFFF SECPPCINTSTAT Secure PPC Interrupt Status 0x20 32 read-only n 0x0 0xFFFFFFFF SECRESPCFG Security Violation Response Configuration register 0x10 32 read-write n 0x0 0xFFFFFFFF SPCSECTRL Secure Privilege Controller Secure Configuration Control register 0x0 32 read-write n 0x0 0xFFFFFFFF SRAM0MPC Memory Protection Controller 0 SRAM_MPC 0x50083000 0x0 0x1000 registers n MPC MPC Combined 9 BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM1MPC SRAM 1 Memory Protection Controller SRAM_MPC 0x50084000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM2MPC SRAM 2 Memory Protection Controller SRAM_MPC 0x50085000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SRAM3MPC SRAM 3 Memory Protection Controller SRAM_MPC 0x50086000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SSP0 SPI 0 SPI 0x41202000 0x0 0x40 registers n SPI0 SPI 0 52 CPSR Clock prescale register 0x10 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 CR0 Control register 0 0x0 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 11-bit None 10 12-bit None 11 13-bit None 12 14-bit None 13 15-bit None 14 16-bit None 15 4-bit None 3 5-bit None 4 6-bit None 5 7-bit None 6 8-bit None 7 9-bit None 8 10-bit None 9 FRF Frame format 4 6 Motorola Motorola SPI frame format 0 TI TI synchronous serial frame format 1 NM National Microwire frame format 2 SCR Serial clock rate 8 16 SPH SSPCLKOUT phase 7 8 SPO SSPCLKOUT polarity 6 7 CR1 Control register 1 0x4 read-write n 0x0 0xFFFFFFFF LBM Loop back mode 0 1 Normal Normal serial port operation enabled 0 Loopback Output of transmit serial shifter is connected to input of receive serial shifter internally 1 MS Master or slave mode select 2 3 Master Device configured as master, default 0 Slave Device configured as slave 1 SOD Slave-mode output disable 3 4 Enable SSP can drive the SSPTXD output in slave mode 0 Disable SSP must not drive the SSPTXD output in slave mode 1 SSE Synchronous serial port enable 1 2 Disabled SSP operation disabled 0 Enabled SSP operation enabled 1 DMACR DMA control register 0x24 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable 0 1 TXDMAE Transmit DMA Enable 1 2 DR Data register 0x8 read-write n 0x0 0xFFFFFFFF Data Transmit/Receive FIFO 0 16 ICR Interrupt clear register 0x20 read-write n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 RTIC Clears the SSPRTINTR interrupt 1 2 IMSC Interrupt mask set or clear register 0x14 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 Masked Receive FIFO written to while full condition interrupt is masked 0 Not Masked Receive FIFO written to while full condition interrupt is not masked 1 RTIM Receive timeout interrupt mask 1 2 Masked Receive FIFO not empty or no read prior to timeout period interrupt is masked 0 Not Masked Receive FIFO not empty or no read prior to timeout period interrupt is not masked 1 RXIM Receive FIFO interrupt mask 2 3 Masked Receive FIFO half full or less condition interrupt is masked 0 Not Masked Receive FIFO half full or less condition interrupt is not masked 1 TXIM Transmit FIFO interrupt mask 3 4 Masked Transmit FIFO half empty or less condition interrupt is masked 0 Not Masked Transmit FIFO half empty or less condition interrupt is not masked 1 ITIP Integration test input register 0x84 read-write n 0x0 0xFFFFFFFF CLKIN Return the value of CLKIN primary input 2 3 FSSIN Return the value of FSSIN primary input 1 2 RXD Return the value of RXD primary input 0 1 RXDDMACLR Value to be driven on the intra-chip input 3 4 TXDMACLR Value to be driven on the intra-chip input 4 5 ITOP Integration test output register 0x88 read-write n 0x0 0xFFFFFFFF CLKOUT Value on the CLKOUT line 2 3 CTLOE Value on the OE line 3 4 FSSOUT Value on the FSSOUT line 1 2 INTR Value on the INTR line 9 10 OE Value on the OE line 4 5 RORINTR Value on the RORINTR line 5 6 RTINTR Value on the RTINTR line 6 7 RXDMABREQ Value on the TXDMABREQ line 10 11 RXDMASREQ Value on the TXDMASREQ line 11 12 RXINTR Value on the RXINTR line 7 8 TXD Value on the TXD line 0 1 TXDMABREQ Value on the TXDMABREQ line 12 13 TXDMASREQ Value on the TXDMASREQ line 13 14 TXINTR Value on the TXINTR line 8 9 MIS Masked interrupt status register 0x1C read-write n 0x0 0xFFFFFFFF RORMIS receive over run masked interrupt state 0 1 RTMIS receive timeout masked interrupt state 1 2 RXMIS receive FIFO masked interrupt state 2 3 TXMIS transmit FIFO masked interrupt state 3 4 RIS Raw interrupt status register 0x18 read-write n 0x0 0xFFFFFFFF RORRIS receive over run raw interrupt state 0 1 RTRIS receive timeout raw interrupt state 1 2 RXRIS receive FIFO raw interrupt state 2 3 TXRIS transmit FIFO raw interrupt state 3 4 SR Status register 0xC read-write n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 5 Idle SSP is idle 0 Busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO full 3 4 NF Receive FIFO is not full 0 F Receive FIFO is full 1 RNE Receive FIFO not empty 2 3 E Receive FIFO is empty 0 NE Receive FIFO is not empty 1 TFE Transmit FIFO empty 0 1 NE Receive FIFO is not empty 0 E Receive FIFO is empty 1 TNF Transmit FIFO not full 1 2 F Receive FIFO is full 0 NF Receive FIFO is not full 1 TCR Test control register 0x80 read-write n 0x0 0xFFFFFFFF ITEN Integration test enable 0 1 Disabled Normal mode 0 Enabled The PrimeCell SSP is placed in integration test mode. 1 TESTFIFO Test FIFO enable 1 2 Disabled Normal operation 0 Enabled When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO. 1 TDR Test data register 0x8C read-write n 0x0 0xFFFFFFFF DATA When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO 0 16 SSP0_Secure SPI 0 (Secure) SPI 0x51202000 0x0 0x40 registers n CPSR Clock prescale register 0x10 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 CR0 Control register 0 0x0 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 11-bit None 10 12-bit None 11 13-bit None 12 14-bit None 13 15-bit None 14 16-bit None 15 4-bit None 3 5-bit None 4 6-bit None 5 7-bit None 6 8-bit None 7 9-bit None 8 10-bit None 9 FRF Frame format 4 6 Motorola Motorola SPI frame format 0 TI TI synchronous serial frame format 1 NM National Microwire frame format 2 SCR Serial clock rate 8 16 SPH SSPCLKOUT phase 7 8 SPO SSPCLKOUT polarity 6 7 CR1 Control register 1 0x4 read-write n 0x0 0xFFFFFFFF LBM Loop back mode 0 1 Normal Normal serial port operation enabled 0 Loopback Output of transmit serial shifter is connected to input of receive serial shifter internally 1 MS Master or slave mode select 2 3 Master Device configured as master, default 0 Slave Device configured as slave 1 SOD Slave-mode output disable 3 4 Enable SSP can drive the SSPTXD output in slave mode 0 Disable SSP must not drive the SSPTXD output in slave mode 1 SSE Synchronous serial port enable 1 2 Disabled SSP operation disabled 0 Enabled SSP operation enabled 1 DMACR DMA control register 0x24 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable 0 1 TXDMAE Transmit DMA Enable 1 2 DR Data register 0x8 read-write n 0x0 0xFFFFFFFF Data Transmit/Receive FIFO 0 16 ICR Interrupt clear register 0x20 read-write n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 RTIC Clears the SSPRTINTR interrupt 1 2 IMSC Interrupt mask set or clear register 0x14 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 Masked Receive FIFO written to while full condition interrupt is masked 0 Not Masked Receive FIFO written to while full condition interrupt is not masked 1 RTIM Receive timeout interrupt mask 1 2 Masked Receive FIFO not empty or no read prior to timeout period interrupt is masked 0 Not Masked Receive FIFO not empty or no read prior to timeout period interrupt is not masked 1 RXIM Receive FIFO interrupt mask 2 3 Masked Receive FIFO half full or less condition interrupt is masked 0 Not Masked Receive FIFO half full or less condition interrupt is not masked 1 TXIM Transmit FIFO interrupt mask 3 4 Masked Transmit FIFO half empty or less condition interrupt is masked 0 Not Masked Transmit FIFO half empty or less condition interrupt is not masked 1 ITIP Integration test input register 0x84 read-write n 0x0 0xFFFFFFFF CLKIN Return the value of CLKIN primary input 2 3 FSSIN Return the value of FSSIN primary input 1 2 RXD Return the value of RXD primary input 0 1 RXDDMACLR Value to be driven on the intra-chip input 3 4 TXDMACLR Value to be driven on the intra-chip input 4 5 ITOP Integration test output register 0x88 read-write n 0x0 0xFFFFFFFF CLKOUT Value on the CLKOUT line 2 3 CTLOE Value on the OE line 3 4 FSSOUT Value on the FSSOUT line 1 2 INTR Value on the INTR line 9 10 OE Value on the OE line 4 5 RORINTR Value on the RORINTR line 5 6 RTINTR Value on the RTINTR line 6 7 RXDMABREQ Value on the TXDMABREQ line 10 11 RXDMASREQ Value on the TXDMASREQ line 11 12 RXINTR Value on the RXINTR line 7 8 TXD Value on the TXD line 0 1 TXDMABREQ Value on the TXDMABREQ line 12 13 TXDMASREQ Value on the TXDMASREQ line 13 14 TXINTR Value on the TXINTR line 8 9 MIS Masked interrupt status register 0x1C read-write n 0x0 0xFFFFFFFF RORMIS receive over run masked interrupt state 0 1 RTMIS receive timeout masked interrupt state 1 2 RXMIS receive FIFO masked interrupt state 2 3 TXMIS transmit FIFO masked interrupt state 3 4 RIS Raw interrupt status register 0x18 read-write n 0x0 0xFFFFFFFF RORRIS receive over run raw interrupt state 0 1 RTRIS receive timeout raw interrupt state 1 2 RXRIS receive FIFO raw interrupt state 2 3 TXRIS transmit FIFO raw interrupt state 3 4 SR Status register 0xC read-write n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 5 Idle SSP is idle 0 Busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO full 3 4 NF Receive FIFO is not full 0 F Receive FIFO is full 1 RNE Receive FIFO not empty 2 3 E Receive FIFO is empty 0 NE Receive FIFO is not empty 1 TFE Transmit FIFO empty 0 1 NE Receive FIFO is not empty 0 E Receive FIFO is empty 1 TNF Transmit FIFO not full 1 2 F Receive FIFO is full 0 NF Receive FIFO is not full 1 TCR Test control register 0x80 read-write n 0x0 0xFFFFFFFF ITEN Integration test enable 0 1 Disabled Normal mode 0 Enabled The PrimeCell SSP is placed in integration test mode. 1 TESTFIFO Test FIFO enable 1 2 Disabled Normal operation 0 Enabled When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO. 1 TDR Test data register 0x8C read-write n 0x0 0xFFFFFFFF DATA When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO 0 16 SSP1 SPI 1 SPI 0x41203000 0x0 0x40 registers n SPI1 SPI 1 53 CPSR Clock prescale register 0x10 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 CR0 Control register 0 0x0 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 11-bit None 10 12-bit None 11 13-bit None 12 14-bit None 13 15-bit None 14 16-bit None 15 4-bit None 3 5-bit None 4 6-bit None 5 7-bit None 6 8-bit None 7 9-bit None 8 10-bit None 9 FRF Frame format 4 6 Motorola Motorola SPI frame format 0 TI TI synchronous serial frame format 1 NM National Microwire frame format 2 SCR Serial clock rate 8 16 SPH SSPCLKOUT phase 7 8 SPO SSPCLKOUT polarity 6 7 CR1 Control register 1 0x4 read-write n 0x0 0xFFFFFFFF LBM Loop back mode 0 1 Normal Normal serial port operation enabled 0 Loopback Output of transmit serial shifter is connected to input of receive serial shifter internally 1 MS Master or slave mode select 2 3 Master Device configured as master, default 0 Slave Device configured as slave 1 SOD Slave-mode output disable 3 4 Enable SSP can drive the SSPTXD output in slave mode 0 Disable SSP must not drive the SSPTXD output in slave mode 1 SSE Synchronous serial port enable 1 2 Disabled SSP operation disabled 0 Enabled SSP operation enabled 1 DMACR DMA control register 0x24 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable 0 1 TXDMAE Transmit DMA Enable 1 2 DR Data register 0x8 read-write n 0x0 0xFFFFFFFF Data Transmit/Receive FIFO 0 16 ICR Interrupt clear register 0x20 read-write n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 RTIC Clears the SSPRTINTR interrupt 1 2 IMSC Interrupt mask set or clear register 0x14 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 Masked Receive FIFO written to while full condition interrupt is masked 0 Not Masked Receive FIFO written to while full condition interrupt is not masked 1 RTIM Receive timeout interrupt mask 1 2 Masked Receive FIFO not empty or no read prior to timeout period interrupt is masked 0 Not Masked Receive FIFO not empty or no read prior to timeout period interrupt is not masked 1 RXIM Receive FIFO interrupt mask 2 3 Masked Receive FIFO half full or less condition interrupt is masked 0 Not Masked Receive FIFO half full or less condition interrupt is not masked 1 TXIM Transmit FIFO interrupt mask 3 4 Masked Transmit FIFO half empty or less condition interrupt is masked 0 Not Masked Transmit FIFO half empty or less condition interrupt is not masked 1 ITIP Integration test input register 0x84 read-write n 0x0 0xFFFFFFFF CLKIN Return the value of CLKIN primary input 2 3 FSSIN Return the value of FSSIN primary input 1 2 RXD Return the value of RXD primary input 0 1 RXDDMACLR Value to be driven on the intra-chip input 3 4 TXDMACLR Value to be driven on the intra-chip input 4 5 ITOP Integration test output register 0x88 read-write n 0x0 0xFFFFFFFF CLKOUT Value on the CLKOUT line 2 3 CTLOE Value on the OE line 3 4 FSSOUT Value on the FSSOUT line 1 2 INTR Value on the INTR line 9 10 OE Value on the OE line 4 5 RORINTR Value on the RORINTR line 5 6 RTINTR Value on the RTINTR line 6 7 RXDMABREQ Value on the TXDMABREQ line 10 11 RXDMASREQ Value on the TXDMASREQ line 11 12 RXINTR Value on the RXINTR line 7 8 TXD Value on the TXD line 0 1 TXDMABREQ Value on the TXDMABREQ line 12 13 TXDMASREQ Value on the TXDMASREQ line 13 14 TXINTR Value on the TXINTR line 8 9 MIS Masked interrupt status register 0x1C read-write n 0x0 0xFFFFFFFF RORMIS receive over run masked interrupt state 0 1 RTMIS receive timeout masked interrupt state 1 2 RXMIS receive FIFO masked interrupt state 2 3 TXMIS transmit FIFO masked interrupt state 3 4 RIS Raw interrupt status register 0x18 read-write n 0x0 0xFFFFFFFF RORRIS receive over run raw interrupt state 0 1 RTRIS receive timeout raw interrupt state 1 2 RXRIS receive FIFO raw interrupt state 2 3 TXRIS transmit FIFO raw interrupt state 3 4 SR Status register 0xC read-write n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 5 Idle SSP is idle 0 Busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO full 3 4 NF Receive FIFO is not full 0 F Receive FIFO is full 1 RNE Receive FIFO not empty 2 3 E Receive FIFO is empty 0 NE Receive FIFO is not empty 1 TFE Transmit FIFO empty 0 1 NE Receive FIFO is not empty 0 E Receive FIFO is empty 1 TNF Transmit FIFO not full 1 2 F Receive FIFO is full 0 NF Receive FIFO is not full 1 TCR Test control register 0x80 read-write n 0x0 0xFFFFFFFF ITEN Integration test enable 0 1 Disabled Normal mode 0 Enabled The PrimeCell SSP is placed in integration test mode. 1 TESTFIFO Test FIFO enable 1 2 Disabled Normal operation 0 Enabled When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO. 1 TDR Test data register 0x8C read-write n 0x0 0xFFFFFFFF DATA When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO 0 16 SSP1_Secure SPI 1 (Secure) GPDMA 0x51203000 0x0 0x55 registers n CFGH Configuration Register High 0x44 32 read-write n 0x0 0xFFFFFFFF DEST_PER Destination Peripheral 11 3 read-write FCMODE Flow Control Mode 0 read-write value1 Source transaction requests are serviced when they occur. Data pre-fetching is enabled. #0 value2 Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. #1 FIFO_MODE FIFO Mode Select 1 read-write value1 Space/data available for single AHB transfer of the specified transfer width. #0 value2 Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. #1 PROTCTL Protection Control 2 2 read-write SRC_PER Source Peripheral 7 3 read-write CFGL Configuration Register Low 0x40 32 read-write n 0x0 0xFFFFFF0F CH_PRIOR Channel priority 5 2 read-write CH_SUSP Channel Suspend 8 read-write value1 Not suspended. #0 value2 Suspend DMA transfer from the source. #1 DST_HS_POL Destination Handshaking Interface Polarity 18 read-write value1 Active high #0 value2 Active low #1 FIFO_EMPTY Indicates if there is data left in the channel FIFO 9 read-only value2 Channel FIFO not empty #0 value1 Channel FIFO empty #1 HS_SEL_DST Destination Software or Hardware Handshaking Select 10 read-write value1 Hardware handshaking interface. Software-initiated transaction requests are ignored. #0 value2 Software handshaking interface. Hardware- initiated transaction requests are ignored. #1 HS_SEL_SRC Source Software or Hardware Handshaking Select 11 read-write value1 Hardware handshaking interface. Software-initiated transaction requests are ignored. #0 value2 Software handshaking interface. Hardware-initiated transaction requests are ignored. #1 LOCK_B Bus Lock Bit 17 read-write LOCK_B_L Bus Lock Level 14 1 read-write value1 Over complete DMA transfer #00 value2 Over complete DMA block transfer #01 value3 Over complete DMA transaction #10 LOCK_CH Channel Lock Bit 16 read-write LOCK_CH_L Channel Lock Level 12 1 read-write value1 Over complete DMA transfer #00 value2 Over complete DMA block transfer #01 value3 Over complete DMA transaction #10 MAX_ABRST Maximum AMBA Burst Length 20 9 read-write SRC_HS_POL Source Handshaking Interface Polarity 19 read-write value1 Active high #0 value2 Active low #1 CTLH Control Register High 0x1C 32 read-write n 0x0 0xFFFFFFFF BLOCK_TS Block Transfer Size 0 11 read-write DONE Done bit 12 read-write CTLL Control Register Low 0x18 32 read-write n 0x0 0xFFFFFFFF DEST_MSIZE Destination Burst Transaction Length 11 2 read-write DINC Destination Address Increment 7 1 read-write value1 Increment #00 value2 Decrement #01 value3 No change #10 DST_TR_WIDTH Destination Transfer Width 1 2 read-write INT_EN Interrupt Enable Bit 0 read-write SINC Source Address Increment 9 1 read-write value1 Increment #00 value2 Decrement #01 value3 No change #10 SRC_MSIZE Source Burst Transaction Length 14 2 read-write SRC_TR_WIDTH Source Transfer Width 4 2 read-write TT_FC Transfer Type and Flow Control 20 2 read-write DAR Destination Address Register 0x8 32 read-write n 0x0 0xFFFFFFFF DAR Current Destination address of DMA transfer 0 31 read-write SAR Source Address Register 0x0 32 read-write n 0x0 0xFFFFFFFF SAR Current Source Address of DMA transfer 0 31 read-write SSP2 SPI 2 SPI 0x41204000 0x0 0x40 registers n SPI2 SPI 2 54 CPSR Clock prescale register 0x10 read-write n 0x0 0xFFFFFFFF CPSDVSR Clock prescale divisor 0 8 CR0 Control register 0 0x0 read-write n 0x0 0xFFFFFFFF DSS Data Size Select 0 4 11-bit None 10 12-bit None 11 13-bit None 12 14-bit None 13 15-bit None 14 16-bit None 15 4-bit None 3 5-bit None 4 6-bit None 5 7-bit None 6 8-bit None 7 9-bit None 8 10-bit None 9 FRF Frame format 4 6 Motorola Motorola SPI frame format 0 TI TI synchronous serial frame format 1 NM National Microwire frame format 2 SCR Serial clock rate 8 16 SPH SSPCLKOUT phase 7 8 SPO SSPCLKOUT polarity 6 7 CR1 Control register 1 0x4 read-write n 0x0 0xFFFFFFFF LBM Loop back mode 0 1 Normal Normal serial port operation enabled 0 Loopback Output of transmit serial shifter is connected to input of receive serial shifter internally 1 MS Master or slave mode select 2 3 Master Device configured as master, default 0 Slave Device configured as slave 1 SOD Slave-mode output disable 3 4 Enable SSP can drive the SSPTXD output in slave mode 0 Disable SSP must not drive the SSPTXD output in slave mode 1 SSE Synchronous serial port enable 1 2 Disabled SSP operation disabled 0 Enabled SSP operation enabled 1 DMACR DMA control register 0x24 read-write n 0x0 0xFFFFFFFF RXDMAE Receive DMA Enable 0 1 TXDMAE Transmit DMA Enable 1 2 DR Data register 0x8 read-write n 0x0 0xFFFFFFFF Data Transmit/Receive FIFO 0 16 ICR Interrupt clear register 0x20 read-write n 0x0 0xFFFFFFFF RORIC Clears the SSPRORINTR interrupt 0 1 RTIC Clears the SSPRTINTR interrupt 1 2 IMSC Interrupt mask set or clear register 0x14 read-write n 0x0 0xFFFFFFFF RORIM Receive overrun interrupt mask 0 1 Masked Receive FIFO written to while full condition interrupt is masked 0 Not Masked Receive FIFO written to while full condition interrupt is not masked 1 RTIM Receive timeout interrupt mask 1 2 Masked Receive FIFO not empty or no read prior to timeout period interrupt is masked 0 Not Masked Receive FIFO not empty or no read prior to timeout period interrupt is not masked 1 RXIM Receive FIFO interrupt mask 2 3 Masked Receive FIFO half full or less condition interrupt is masked 0 Not Masked Receive FIFO half full or less condition interrupt is not masked 1 TXIM Transmit FIFO interrupt mask 3 4 Masked Transmit FIFO half empty or less condition interrupt is masked 0 Not Masked Transmit FIFO half empty or less condition interrupt is not masked 1 ITIP Integration test input register 0x84 read-write n 0x0 0xFFFFFFFF CLKIN Return the value of CLKIN primary input 2 3 FSSIN Return the value of FSSIN primary input 1 2 RXD Return the value of RXD primary input 0 1 RXDDMACLR Value to be driven on the intra-chip input 3 4 TXDMACLR Value to be driven on the intra-chip input 4 5 ITOP Integration test output register 0x88 read-write n 0x0 0xFFFFFFFF CLKOUT Value on the CLKOUT line 2 3 CTLOE Value on the OE line 3 4 FSSOUT Value on the FSSOUT line 1 2 INTR Value on the INTR line 9 10 OE Value on the OE line 4 5 RORINTR Value on the RORINTR line 5 6 RTINTR Value on the RTINTR line 6 7 RXDMABREQ Value on the TXDMABREQ line 10 11 RXDMASREQ Value on the TXDMASREQ line 11 12 RXINTR Value on the RXINTR line 7 8 TXD Value on the TXD line 0 1 TXDMABREQ Value on the TXDMABREQ line 12 13 TXDMASREQ Value on the TXDMASREQ line 13 14 TXINTR Value on the TXINTR line 8 9 MIS Masked interrupt status register 0x1C read-write n 0x0 0xFFFFFFFF RORMIS receive over run masked interrupt state 0 1 RTMIS receive timeout masked interrupt state 1 2 RXMIS receive FIFO masked interrupt state 2 3 TXMIS transmit FIFO masked interrupt state 3 4 RIS Raw interrupt status register 0x18 read-write n 0x0 0xFFFFFFFF RORRIS receive over run raw interrupt state 0 1 RTRIS receive timeout raw interrupt state 1 2 RXRIS receive FIFO raw interrupt state 2 3 TXRIS transmit FIFO raw interrupt state 3 4 SR Status register 0xC read-write n 0x0 0xFFFFFFFF BSY PrimeCell SSP busy flag 4 5 Idle SSP is idle 0 Busy SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty 1 RFF Receive FIFO full 3 4 NF Receive FIFO is not full 0 F Receive FIFO is full 1 RNE Receive FIFO not empty 2 3 E Receive FIFO is empty 0 NE Receive FIFO is not empty 1 TFE Transmit FIFO empty 0 1 NE Receive FIFO is not empty 0 E Receive FIFO is empty 1 TNF Transmit FIFO not full 1 2 F Receive FIFO is full 0 NF Receive FIFO is not full 1 TCR Test control register 0x80 read-write n 0x0 0xFFFFFFFF ITEN Integration test enable 0 1 Disabled Normal mode 0 Enabled The PrimeCell SSP is placed in integration test mode. 1 TESTFIFO Test FIFO enable 1 2 Disabled Normal operation 0 Enabled When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO. 1 TDR Test data register 0x8C read-write n 0x0 0xFFFFFFFF DATA When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO 0 16 SSP2_Secure SPI 2 (Secure) GPDMA 0x51204000 0x0 0x7D40 registers n CHENREG GPDMA Channel Enable Register 0xE0 32 read-write n 0x0 0xFFFFFFFF CH Enables/Disables the channel 0 3 read-write value1 Disable the Channel #0 value2 Enable the Channel #1 WE_CH Channel enable write enable 8 3 write-only CLEARBLOCK IntBlock Status 0x80 32 read-write n 0x0 0xFFFFFFFF CH0 Clear Interrupt Status and Raw Status for channel 0 0 write-only value1 no effect #0 value2 clear status #1 CH1 Clear Interrupt Status and Raw Status for channel 1 1 write-only value1 no effect #0 value2 clear status #1 CH2 Clear Interrupt Status and Raw Status for channel 2 2 write-only value1 no effect #0 value2 clear status #1 CH3 Clear Interrupt Status and Raw Status for channel 3 3 write-only value1 no effect #0 value2 clear status #1 CLEARDSTTRAN IntBlock Status 0x90 32 read-write n 0x0 0xFFFFFFFF CH0 Clear Interrupt Status and Raw Status for channel 0 0 write-only value1 no effect #0 value2 clear status #1 CH1 Clear Interrupt Status and Raw Status for channel 1 1 write-only value1 no effect #0 value2 clear status #1 CH2 Clear Interrupt Status and Raw Status for channel 2 2 write-only value1 no effect #0 value2 clear status #1 CH3 Clear Interrupt Status and Raw Status for channel 3 3 write-only value1 no effect #0 value2 clear status #1 CLEARERR IntErr Status 0x98 32 read-write n 0x0 0xFFFFFFFF CH0 Clear Interrupt Status and Raw Status for channel 0 0 write-only value1 no effect #0 value2 clear status #1 CH1 Clear Interrupt Status and Raw Status for channel 1 1 write-only value1 no effect #0 value2 clear status #1 CH2 Clear Interrupt Status and Raw Status for channel 2 2 write-only value1 no effect #0 value2 clear status #1 CH3 Clear Interrupt Status and Raw Status for channel 3 3 write-only value1 no effect #0 value2 clear status #1 CLEARSRCTRAN IntSrcTran Status 0x88 32 read-write n 0x0 0xFFFFFFFF CH0 Clear Interrupt Status and Raw Status for channel 0 0 write-only value1 no effect #0 value2 clear status #1 CH1 Clear Interrupt Status and Raw Status for channel 1 1 write-only value1 no effect #0 value2 clear status #1 CH2 Clear Interrupt Status and Raw Status for channel 2 2 write-only value1 no effect #0 value2 clear status #1 CH3 Clear Interrupt Status and Raw Status for channel 3 3 write-only value1 no effect #0 value2 clear status #1 CLEARTFR IntTfr Status 0x78 32 read-write n 0x0 0xFFFFFFFF CH0 Clear Interrupt Status and Raw Status for channel 0 0 write-only value1 no effect #0 value2 clear status #1 CH1 Clear Interrupt Status and Raw Status for channel 1 1 write-only value1 no effect #0 value2 clear status #1 CH2 Clear Interrupt Status and Raw Status for channel 2 2 write-only value1 no effect #0 value2 clear status #1 CH3 Clear Interrupt Status and Raw Status for channel 3 3 write-only value1 no effect #0 value2 clear status #1 DMACFGREG GPDMA Configuration Register 0xD8 32 read-write n 0x0 0xFFFFFFFF DMA_EN GPDMA Enable bit. 0 read-write value1 GPDMA Disabled #0 value2 GPDMA Enabled. #1 ID GPDMA1 ID Register 0xE8 32 read-write n 0x0 0xFFFFFF00 VALUE Hardcoded GPDMA Peripheral ID 0 31 read-only LSTDSTREG Last Destination Transaction Request Register 0xD0 32 read-write n 0x0 0xFFFFFFFF CH0 Destination last request for channel 0 0 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH1 Destination last request for channel 1 1 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH2 Destination last request for channel 2 2 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH3 Destination last request for channel 3 3 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 WE_CH0 Destination last transaction request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Destination last transaction request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Destination last transaction request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Destination last transaction request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 LSTSRCREG Last Source Transaction Request Register 0xC8 32 read-write n 0x0 0xFFFFFFFF CH0 Source last request for channel 0 0 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH1 Source last request for channel 1 1 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH2 Source last request for channel 2 2 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 CH3 Source last request for channel 3 3 read-write value1 Not last transaction in current block #0 value2 Last transaction in current block #1 WE_CH0 Source last transaction request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Source last transaction request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Source last transaction request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Source last transaction request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 MASKBLOCK Mask for Raw IntBlock Status 0x58 32 read-write n 0x0 0xFFFFFFFF CH0 Mask bit for channel 0 0 read-write value1 masked #0 value2 unmasked #1 CH1 Mask bit for channel 1 1 read-write value1 masked #0 value2 unmasked #1 CH2 Mask bit for channel 2 2 read-write value1 masked #0 value2 unmasked #1 CH3 Mask bit for channel 3 3 read-write value1 masked #0 value2 unmasked #1 WE_CH0 Write enable for mask bit of channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Write enable for mask bit of channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Write enable for mask bit of channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Write enable for mask bit of channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 MASKDSTTRAN Mask for Raw IntBlock Status 0x68 32 read-write n 0x0 0xFFFFFFFF CH0 Mask bit for channel 0 0 read-write value1 masked #0 value2 unmasked #1 CH1 Mask bit for channel 1 1 read-write value1 masked #0 value2 unmasked #1 CH2 Mask bit for channel 2 2 read-write value1 masked #0 value2 unmasked #1 CH3 Mask bit for channel 3 3 read-write value1 masked #0 value2 unmasked #1 WE_CH0 Write enable for mask bit of channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Write enable for mask bit of channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Write enable for mask bit of channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Write enable for mask bit of channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 MASKERR Mask for Raw IntErr Status 0x70 32 read-write n 0x0 0xFFFFFFFF CH0 Mask bit for channel 0 0 read-write value1 masked #0 value2 unmasked #1 CH1 Mask bit for channel 1 1 read-write value1 masked #0 value2 unmasked #1 CH2 Mask bit for channel 2 2 read-write value1 masked #0 value2 unmasked #1 CH3 Mask bit for channel 3 3 read-write value1 masked #0 value2 unmasked #1 WE_CH0 Write enable for mask bit of channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Write enable for mask bit of channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Write enable for mask bit of channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Write enable for mask bit of channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 MASKSRCTRAN Mask for Raw IntSrcTran Status 0x60 32 read-write n 0x0 0xFFFFFFFF CH0 Mask bit for channel 0 0 read-write value1 masked #0 value2 unmasked #1 CH1 Mask bit for channel 1 1 read-write value1 masked #0 value2 unmasked #1 CH2 Mask bit for channel 2 2 read-write value1 masked #0 value2 unmasked #1 CH3 Mask bit for channel 3 3 read-write value1 masked #0 value2 unmasked #1 WE_CH0 Write enable for mask bit of channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Write enable for mask bit of channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Write enable for mask bit of channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Write enable for mask bit of channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 MASKTFR Mask for Raw IntTfr Status 0x50 32 read-write n 0x0 0xFFFFFFFF CH0 Mask bit for channel 0 0 read-write value1 masked #0 value2 unmasked #1 CH1 Mask bit for channel 1 1 read-write value1 masked #0 value2 unmasked #1 CH2 Mask bit for channel 2 2 read-write value1 masked #0 value2 unmasked #1 CH3 Mask bit for channel 3 3 read-write value1 masked #0 value2 unmasked #1 WE_CH0 Write enable for mask bit of channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Write enable for mask bit of channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Write enable for mask bit of channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Write enable for mask bit of channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 RAWBLOCK Raw IntBlock Status 0x8 32 read-write n 0x0 0xFFFFFFFF CH0 Raw Interrupt Status for channel 0 0 read-write CH1 Raw Interrupt Status for channel 1 1 read-write CH2 Raw Interrupt Status for channel 2 2 read-write CH3 Raw Interrupt Status for channel 3 3 read-write RAWDSTTRAN Raw IntBlock Status 0x18 32 read-write n 0x0 0xFFFFFFFF CH0 Raw Interrupt Status for channel 0 0 read-write CH1 Raw Interrupt Status for channel 1 1 read-write CH2 Raw Interrupt Status for channel 2 2 read-write CH3 Raw Interrupt Status for channel 3 3 read-write RAWERR Raw IntErr Status 0x20 32 read-write n 0x0 0xFFFFFFFF CH0 Raw Interrupt Status for channel 0 0 read-write CH1 Raw Interrupt Status for channel 1 1 read-write CH2 Raw Interrupt Status for channel 2 2 read-write CH3 Raw Interrupt Status for channel 3 3 read-write RAWSRCTRAN Raw IntSrcTran Status 0x10 32 read-write n 0x0 0xFFFFFFFF CH0 Raw Interrupt Status for channel 0 0 read-write CH1 Raw Interrupt Status for channel 1 1 read-write CH2 Raw Interrupt Status for channel 2 2 read-write CH3 Raw Interrupt Status for channel 3 3 read-write RAWTFR Raw IntTfr Status 0x0 32 read-write n 0x0 0xFFFFFFFF CH0 Raw Interrupt Status for channel 0 0 read-write CH1 Raw Interrupt Status for channel 1 1 read-write CH2 Raw Interrupt Status for channel 2 2 read-write CH3 Raw Interrupt Status for channel 3 3 read-write REQDSTREG Destination Software Transaction Request Register 0xB0 32 read-write n 0x0 0xFFFFFFFF CH0 Source request for channel 0 0 read-write CH1 Source request for channel 1 1 read-write CH2 Source request for channel 2 2 read-write CH3 Source request for channel 3 3 read-write WE_CH0 Source request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Source request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Source request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Source request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 REQSRCREG Source Software Transaction Request Register 0xA8 32 read-write n 0x0 0xFFFFFFFF CH0 Source request for channel 0 0 read-write CH1 Source request for channel 1 1 read-write CH2 Source request for channel 2 2 read-write CH3 Source request for channel 3 3 read-write WE_CH0 Source request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Source request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Source request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Source request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 SGLREQDSTREG Single Destination Transaction Request Register 0xC0 32 read-write n 0x0 0xFFFFFFFF CH0 Source request for channel 0 0 read-write CH1 Source request for channel 1 1 read-write CH2 Source request for channel 2 2 read-write CH3 Source request for channel 3 3 read-write WE_CH0 Source request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Source request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Source request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Source request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 SGLREQSRCREG Single Source Transaction Request Register 0xB8 32 read-write n 0x0 0xFFFFFFFF CH0 Source request for channel 0 0 read-write CH1 Source request for channel 1 1 read-write CH2 Source request for channel 2 2 read-write CH3 Source request for channel 3 3 read-write WE_CH0 Source request write enable for channel 0 8 write-only value1 write disabled #0 value2 write enabled #1 WE_CH1 Source request write enable for channel 1 9 write-only value1 write disabled #0 value2 write enabled #1 WE_CH2 Source request write enable for channel 2 10 write-only value1 write disabled #0 value2 write enabled #1 WE_CH3 Source request write enable for channel 3 11 write-only value1 write disabled #0 value2 write enabled #1 STATUSBLOCK IntBlock Status 0x30 32 read-write n 0x0 0xFFFFFFFF CH0 Interrupt Status for channel 0 0 read-only CH1 Interrupt Status for channel 1 1 read-only CH2 Interrupt Status for channel 2 2 read-only CH3 Interrupt Status for channel 3 3 read-only STATUSDSTTRAN IntBlock Status 0x40 32 read-write n 0x0 0xFFFFFFFF CH0 Interrupt Status for channel 0 0 read-only CH1 Interrupt Status for channel 1 1 read-only CH2 Interrupt Status for channel 2 2 read-only CH3 Interrupt Status for channel 3 3 read-only STATUSERR IntErr Status 0x48 32 read-write n 0x0 0xFFFFFFFF CH0 Interrupt Status for channel 0 0 read-only CH1 Interrupt Status for channel 1 1 read-only CH2 Interrupt Status for channel 2 2 read-only CH3 Interrupt Status for channel 3 3 read-only STATUSINT Combined Interrupt Status Register 0xA0 32 read-write n 0x0 0xFFFFFFFF BLOCK OR of the contents of STATUSBLOCK register 1 read-only DSTT OR of the contents of STATUSDSTTRAN register 3 read-only ERR OR of the contents of STATUSERR register 4 read-only SRCT OR of the contents of STATUSSRCTRAN register 2 read-only TFR OR of the contents of STATUSTFR register 0 read-only STATUSSRCTRAN IntSrcTran Status 0x38 32 read-write n 0x0 0xFFFFFFFF CH0 Interrupt Status for channel 0 0 read-only CH1 Interrupt Status for channel 1 1 read-only CH2 Interrupt Status for channel 2 2 read-only CH3 Interrupt Status for channel 3 3 read-only STATUSTFR IntTfr Status 0x28 32 read-write n 0x0 0xFFFFFFFF CH0 Interrupt Status for channel 0 0 read-only CH1 Interrupt Status for channel 1 1 read-only CH2 Interrupt Status for channel 2 2 read-only CH3 Interrupt Status for channel 3 3 read-only TYPE GPDMA Component Type 0x138 32 read-write n 0x0 0xFFFFFFFF VALUE Component Type 0 31 read-only VERSION DMA Component Version 0x13C 32 read-write n 0x0 0xFFFFFFFF VALUE Version number of the component 0 31 read-only SSRAM1MPC SSRAM 1 Memory Protection Controller SRAM_MPC 0x58007000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SSRAM2MPC SSRAM 2 Memory Protection Controller SRAM_MPC 0x58008000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF SSRAM3MPC SSRAM 3 Memory Protection Controller SRAM_MPC 0x58009000 0x0 0x1000 registers n BLK_CFG Block Configuration 0x14 32 read-only n 0x0 0xFFFFFFFF BLK_IDX Index value for accessing block based look up table 0x18 32 read-write n 0x0 0xFFFFFFFF BLK_LUT Block based gating Look Up Table 0x1C 32 read-write n 0x0 0xFFFFFFFF BLK_MAX Maximum value of block based index register 0x10 32 read-only n 0x0 0xFFFFFFFF bit[31] Initialization in progress 31 1 bit[3_0] Block size 0 4 CIDR0 Component ID 0 0xFF0 32 read-only n 0xD 0xFFFFFFFF CIDR1 Component ID 1 0xFF4 32 read-only n 0xF0 0xFFFFFFFF CIDR2 Component ID 2 0xFF8 32 read-only n 0x5 0xFFFFFFFF CIDR3 Component ID 3 0xFFC 32 read-only n 0xB1 0xFFFFFFFF CTRL MPC Control register 0x0 32 read-write n 0x0 0xFFFFFFFF bit[31] Security lockdown 31 1 bit[4] Security error response configuration 4 1 RAZ-WI Read-As-Zero - Writes ignored 0 BUSERROR Bus Error 1 bit[6] Data interface gating request 6 1 bit[7] Data interface gating acknowledge (RO) 7 1 bit[8] Auto-increment 8 1 INT_CLEAR Interrupt clear 0x24 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq clear (cleared automatically) 0 1 INT_EN Interrupt enable 0x28 32 read-write n 0x0 0xFFFFFFFF bit[0] mpc_irq enable. Bits are valid when mpc_irq triggered is set 0 1 INT_INFO1 Interrupt information 1 0x2C 32 read-only n 0x0 0xFFFFFFFF INT_INFO2 Interrupt information 2 0x30 32 read-only n 0x0 0xFFFFFFFF bit[15_0] hmaster 0 16 bit[16] hnonsec 16 1 bit[17] cfg_ns 17 1 INT_SET Interrupt set. Debug purpose only 0x34 32 write-only n 0x0 0xFFFFFFFF bit[0] mpc_irq set. Debug purpose only 0 1 INT_STAT Interrupt state 0x20 32 read-only n 0x0 0xFFFFFFFF bit[0] mpc_irq triggered 0 1 PIDR0 Peripheral ID 0 0xFE0 32 read-only n 0x60 0xFFFFFFFF PIDR1 Peripheral ID 1 0xFE4 32 read-only n 0xB8 0xFFFFFFFF PIDR2 Peripheral ID 2 0xFE8 32 read-only n 0xB 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR3 Peripheral ID 3 0xFEC 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Customer modification number 0 4 bit[7_4] ECO revision number 4 4 PIDR4 Peripheral ID 4 0xFD0 32 read-only n 0x4 0xFFFFFFFF bit[3_0] jep106_c_code 0 4 bit[7_4] block count 4 4 PIDR5 Peripheral ID 5 0xFD4 32 read-only n 0x0 0xFFFFFFFF bit[3_0] Part number 0 4 bit[7_4] jep106_id_3_0 4 4 PIDR6 Peripheral ID 6 0xFD8 32 read-only n 0x0 0xFFFFFFFF PIDR7 Peripheral ID 7 0xFDC 32 read-only n 0x0 0xFFFFFFFF TIMER0 Timer 0 Timer 0x40000000 0x0 0x10 registers n TIMER0 Timer 0 3 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER0_Secure Timer 0 (Secure) Timer 0x50000000 0x0 0x10 registers n CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1 Timer 1 Timer 0x40001000 0x0 0x10 registers n TIMER1 Timer 1 4 CTRL Control Register 0x0 read-write n 0x0 0xFFFFFFFF ENABLE Enable 0 1 Disable Timer is disabled 0 Enable Timer is enabled 1 EXTCLK External Clock Enable 2 3 Disable External Clock is disabled 0 Enable External Clock is enabled 1 EXTIN External Input as Enable 1 2 Disable External Input as Enable is disabled 0 Enable External Input as Enable is enabled 1 INTEN Interrupt Enable 3 4 Disable Interrupt is disabled 0 Enable Interrupt is enabled 1 INTCLEAR Timer Interrupt clear register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF oneToClear INTSTATUS Timer Interrupt status register 0xC read-only n 0x0 0xFFFFFFFF RELOAD Counter Reload Value 0x8 read-write n 0x0 0xFFFFFFFF VALUE Current Timer Counter Value 0x4 read-write n 0x0 0xFFFFFFFF TIMER1_Secure Timer 1 (Secure) VADC 0x50001000 0x0 0x400 registers n ALIAS Alias Register 0xB0 32 read-write n 0x0 0xFFFFFFFF ALIAS0 Alias Value for CH0 Conversion Requests 0 4 read-write ALIAS1 Alias Value for CH1 Conversion Requests 8 4 read-write ARBCFG Arbitration Configuration Register 0x80 32 read-write n 0x0 0xFFFFFFFF ANONC Analog Converter Control 0 1 read-write ANONS Analog Converter Control Status 16 1 read-only value1 Analog converter off #00 value4 Normal operation (permanently on) #11 ARBM Arbitration Mode 7 read-write value1 The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ). #0 value2 The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported. #1 ARBRND Arbitration Round Length 4 1 read-write value1 4 arbitration slots per round (tARB = 4 / fADCD) #00 value2 8 arbitration slots per round (tARB = 8 / fADCD) #01 value3 16 arbitration slots per round (tARB = 16 / fADCD) #10 value4 20 arbitration slots per round (tARB = 20 / fADCD) #11 BUSY Converter Busy Flag 30 read-only value1 Not busy #0 value2 Converter is busy with a conversion #1 CAL Start-Up Calibration Active Indication 28 read-only value1 Completed or not yet started #0 value2 Start-up calibration phase is active #1 SAMPLE Sample Phase Flag 31 read-only value1 Converting or idle #0 value2 Input signal is currently sampled #1 ARBPR Arbitration Priority Register 0x84 32 read-write n 0x0 0xFFFFFFFF ASEN0 Arbitration Slot 0 Enable 24 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 ASEN1 Arbitration Slot 1 Enable 25 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 ASEN2 Arbitration Slot 2 Enable 26 read-write value1 The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded. #0 value2 The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated. #1 CSM0 Conversion Start Mode of Request Source x 3 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 CSM1 Conversion Start Mode of Request Source x 7 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 CSM2 Conversion Start Mode of Request Source x 11 read-write value1 Wait-for-start mode #0 value2 Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources. #1 PRIO0 Priority of Request Source x 0 1 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 PRIO1 Priority of Request Source x 4 1 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 PRIO2 Priority of Request Source x 8 1 read-write value1 Lowest priority is selected. #00 value2 Highest priority is selected. #11 ASCTRL Autoscan Source Control Register 0x120 32 read-write n 0x0 0xFFFFFFFF GTLVL Gate Input Level 20 read-only GTSEL Gate Input Selection 16 3 read-write GTWC Write Control for Gate Configuration 23 write-only value1 No write access to gate configuration #0 value2 Bitfield GTSEL can be written #1 TMEN Timer Mode Enable 28 read-write value1 No timer mode: standard gating mechanism can be used #0 value2 Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled #1 TMWC Write Control for Timer Mode 31 write-only value1 No write access to timer mode #0 value2 Bitfield TMEN can be written #1 XTLVL External Trigger Level 12 read-only XTMODE Trigger Operating Mode 13 1 read-write value1 No external trigger #00 value2 Trigger event upon a falling edge #01 value3 Trigger event upon a rising edge #10 value4 Trigger event upon any edge #11 XTSEL External Trigger Input Selection 8 3 read-write XTWC Write Control for Trigger Configuration 15 write-only value1 No write access to trigger configuration #0 value2 Bitfields XTMODE and XTSEL can be written #1 ASMR Autoscan Source Mode Register 0x124 32 read-write n 0x0 0xFFFFFFFF CLRPND Clear Pending Bits 8 write-only value1 No action #0 value2 The bits in register GxASPNDx are cleared #1 ENGT Enable Gate 0 1 read-write value1 No conversion requests are issued #00 value2 Conversion requests are issued if at least one pending bit is set #01 value3 Conversion requests are issued if at least one pending bit is set and REQGTx = 1. #10 value4 Conversion requests are issued if at least one pending bit is set and REQGTx = 0. #11 ENSI Enable Source Interrupt 3 read-write value1 No request source interrupt #0 value2 A request source interrupt is generated upon a request source event (last pending conversion is finished) #1 ENTR Enable External Trigger 2 read-write value1 External trigger disabled #0 value2 The selected edge at the selected trigger input signal REQTR generates the load event #1 LDEV Generate Load Event 9 write-only value1 No action #0 value2 A load event is generated #1 LDM Autoscan Source Load Event Mode 5 read-write value1 Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event #0 value2 Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR) #1 REQGT Request Gate Level 7 read-only value1 The gate input is low #0 value2 The gate input is high #1 RPTDIS Repeat Disable 16 read-write value1 A cancelled conversion is repeated #0 value2 A cancelled conversion is discarded #1 SCAN Autoscan Enable 4 read-write value1 No autoscan #0 value2 Autoscan functionality enabled: a request source event automatically generates a load event #1 ASPND Autoscan Source Pending Register 0x12C 32 read-write n 0x0 0xFFFFFFFF CHPND0 Channels Pending 0 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND1 Channels Pending 1 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND2 Channels Pending 2 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND3 Channels Pending 3 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND4 Channels Pending 4 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND5 Channels Pending 5 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND6 Channels Pending 6 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 CHPND7 Channels Pending 7 read-write value1 Ignore this channel #0 value2 Request conversion of this channel #1 ASSEL Autoscan Source Channel Select Register 0x128 32 read-write n 0x0 0xFFFFFFFF CHSEL0 Channel Selection 0 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL1 Channel Selection 1 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL2 Channel Selection 2 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL3 Channel Selection 3 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL4 Channel Selection 4 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL5 Channel Selection 5 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL6 Channel Selection 6 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 CHSEL7 Channel Selection 7 read-write value1 Ignore this channel #0 value2 This channel is part of the scan sequence #1 BFL Boundary Flag Register 0xC8 32 read-write n 0x0 0xFFFFFFFF BFE0 Enable Bit for Boundar0 Flag y 16 read-write value1 Output 0 on this channel #0 value2 Output BFLy on this channel #1 BFE1 Enable Bit for Boundar1 Flag y 17 read-write value1 Output 0 on this channel #0 value2 Output BFLy on this channel #1 BFE2 Enable Bit for Boundar2 Flag y 18 read-write value1 Output 0 on this channel #0 value2 Output BFLy on this channel #1 BFE3 Enable Bit for Boundar3 Flag y 19 read-write value1 Output 0 on this channel #0 value2 Output BFLy on this channel #1 BFL0 Boundar0 Flag y 0 read-only value1 Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL1 Boundar1 Flag y 1 read-only value1 Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL2 Boundar2 Flag y 2 read-only value1 Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BFL3 Boundar3 Flag y 3 read-only value1 Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled #0 value2 Active state: result has crossed the activation boundary #1 BOUND Boundary Select Register 0xB8 32 read-write n 0x0 0xFFFFFFFF BOUNDARY0 Boundary Value 0 for Limit Checking 0 11 read-write BOUNDARY1 Boundary Value 1 for Limit Checking 16 11 read-write CEFCLR Channel Event Flag Clear Register 0x190 32 read-write n 0x0 0xFFFFFFFF CEV0 Clear Channel Event for Channel 0 0 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV1 Clear Channel Event for Channel 1 1 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV2 Clear Channel Event for Channel 2 2 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV3 Clear Channel Event for Channel 3 3 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV4 Clear Channel Event for Channel 4 4 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV5 Clear Channel Event for Channel 5 5 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV6 Clear Channel Event for Channel 6 6 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEV7 Clear Channel Event for Channel 7 7 write-only value1 No action #0 value2 Clear the channel event flag in GxCEFLAG #1 CEFLAG Channel Event Flag Register 0x180 32 read-write n 0x0 0xFFFFFFFF CEV0 Channel Event for Channel 0 0 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV1 Channel Event for Channel 1 1 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV2 Channel Event for Channel 2 2 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV3 Channel Event for Channel 3 3 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV4 Channel Event for Channel 4 4 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV5 Channel Event for Channel 5 5 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV6 Channel Event for Channel 6 6 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEV7 Channel Event for Channel 7 7 read-write value1 No channel event #0 value2 A channel event has occurred #1 CEVNP0 Channel Event Node Pointer Register 0 0x1A0 32 read-write n 0x0 0xFFFFFFFF CEV0NP Service Request Node Pointer Channel Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV1NP Service Request Node Pointer Channel Event i 4 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV2NP Service Request Node Pointer Channel Event i 8 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV3NP Service Request Node Pointer Channel Event i 12 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV4NP Service Request Node Pointer Channel Event i 16 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV5NP Service Request Node Pointer Channel Event i 20 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV6NP Service Request Node Pointer Channel Event i 24 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CEV7NP Service Request Node Pointer Channel Event i 28 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 CHASS Channel Assignment Register 0x88 32 read-write n 0x0 0xFFFFFFFF ASSCH0 Assignment for Channel 0 0 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH1 Assignment for Channel 1 1 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH2 Assignment for Channel 2 2 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH3 Assignment for Channel 3 3 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH4 Assignment for Channel 4 4 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH5 Assignment for Channel 5 5 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH6 Assignment for Channel 6 6 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 ASSCH7 Assignment for Channel 7 7 read-write value1 Channel y can be a background channel converted with lowest priority #0 value2 Channel y is a priority channel within group x #1 CHCTR[0] Channel Ctrl. Reg. 0x400 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[1] Channel Ctrl. Reg. 0x604 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[2] Channel Ctrl. Reg. 0x80C 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[3] Channel Ctrl. Reg. 0xA18 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[4] Channel Ctrl. Reg. 0xC28 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[5] Channel Ctrl. Reg. 0xE3C 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[6] Channel Ctrl. Reg. 0x1054 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 CHCTR[7] Channel Ctrl. Reg. 0x1270 32 read-write n 0x0 0xFFFFFFFF BNDSELL Lower Boundary Select 4 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BNDSELU Upper Boundary Select 6 1 read-write value1 Use group-specific boundary 0 #00 value2 Use group-specific boundary 1 #01 value3 Use global boundary 0 #10 value4 Use global boundary 1 #11 BWDCH Broken Wire Detection Channel 28 1 read-write value1 Select VAGND #00 value2 Select VAREF #01 BWDEN Broken Wire Detection Enable 30 read-write value1 Normal operation #0 value2 Additional preparation phase is enabled #1 CHEVMODE Channel Event Mode 8 1 read-write value1 Never #00 value2 NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.) #01 value3 NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.) #10 value4 NCM: Always (ignore band) FCM: If result switches to either level #11 ICLSEL Input Class Select 0 1 read-write value1 Use group-specific class 0 #00 value2 Use group-specific class 1 #01 value3 Use global class 0 #10 value4 Use global class 1 #11 REFSEL Reference Input Selection 11 read-write value1 Standard reference input VAREF #0 value2 Alternate reference input from CH0 #1 RESPOS Result Position 21 read-write value1 Store results left-aligned #0 value2 Store results right-aligned #1 RESREG Result Register 16 3 read-write value1 Store result in group result register GxRES0 #0000 value2 Store result in group result register GxRES15 #1111 RESTBS Result Target for Background Source 20 read-write value1 Store results in the selected group result register #0 value2 Store results in the global result register #1 SYNC Synchronization Request 10 read-write value1 No synchroniz. request, standalone operation #0 value2 Request a synchronized conversion of this channel (only taken into account for a master) #1 EMUXCTR External Multiplexer Control Register 0x1F0 32 read-write n 0x0 0xFFFFFFFF EMUXACT External Multiplexer Actual Selection 8 2 read-only EMUXCH External Multiplexer Channel Select 16 4 read-write EMUXMODE External Multiplexer Mode 26 1 read-write value1 Software control (no hardware action) #00 value2 Steady mode (use EMUXSET value) #01 value3 Single-step mode #10 value4 Sequence mode #11 EMUXSET External Multiplexer Start Selection 0 2 read-write EMXCOD External Multiplexer Coding Scheme 28 read-write value1 Output the channel number in binary code #0 value2 Output the channel number in Gray code #1 EMXST External Multiplexer Sample Time Control 29 read-write value1 Use STCE whenever the setting changes #0 value2 Use STCE for each conversion of an external channel #1 EMXWC Write Control for EMUX Configuration 31 write-only value1 No write access to EMUX cfg. #0 value2 Bitfields EMXMODE, EMXCOD, EMXST can be written #1 ICLASS[0] Input Class Register 0x140 32 read-write n 0x0 0xFFFFFFFF CME Conversion Mode for EMUX Conversions 24 2 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 CMS Conversion Mode for Standard Conversions 8 2 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 STCE Sample Time Control for EMUX Conversions 16 4 read-write STCS Sample Time Control for Standard Conversions 0 4 read-write ICLASS[1] Input Class Register 0x1E4 32 read-write n 0x0 0xFFFFFFFF CME Conversion Mode for EMUX Conversions 24 2 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 CMS Conversion Mode for Standard Conversions 8 2 read-write value1 12-bit conversion #000 value2 10-bit conversion #001 value3 8-bit conversion #010 value6 10-bit fast compare mode #101 STCE Sample Time Control for EMUX Conversions 16 4 read-write STCS Sample Time Control for Standard Conversions 0 4 read-write Q0R0 Queue 0 Register 0 0x10C 32 read-write n 0x0 0xFFFFFFFF ENSI Enable Source Interrupt 6 read-only value1 No request source interrupt #0 value2 A request source event interrupt is generated upon a request source event (related conversion is finished) #1 EXTR External Trigger 7 read-only value1 A valid queue entry immediately leads to a conversion request #0 value2 The request handler waits for a trigger event #1 REQCHNR Request Channel Number 0 4 read-only RF Refill 5 read-only value1 The request is discarded after the conversion start. #0 value2 The request is automatically refilled into the queue after the conversion start. #1 V Request Channel Number Valid 8 read-only value1 No valid queue entry #0 value2 The queue entry is valid and leads to a conversion request #1 QBUR0 Queue 0 Backup Register QINR0 0x110 32 read-write n 0x0 0xFFFFFFFF ENSI Enable Source Interrupt 6 read-only EXTR External Trigger 7 read-only REQCHNR Request Channel Number 0 4 read-only RF Refill 5 read-only V Request Channel Number Valid 8 read-only value1 Backup register not valid #0 value2 Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested. #1 QCTRL0 Queue 0 Source Control Register 0x100 32 read-write n 0x0 0xFFFFFFFF GTLVL Gate Input Level 20 read-only GTSEL Gate Input Selection 16 3 read-write GTWC Write Control for Gate Configuration 23 write-only value1 No write access to gate configuration #0 value2 Bitfield GTSEL can be written #1 TMEN Timer Mode Enable 28 read-write value1 No timer mode: standard gating mechanism can be used #0 value2 Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled #1 TMWC Write Control for Timer Mode 31 write-only value1 No write access to timer mode #0 value2 Bitfield TMEN can be written #1 XTLVL External Trigger Level 12 read-only XTMODE Trigger Operating Mode 13 1 read-write value1 No external trigger #00 value2 Trigger event upon a falling edge #01 value3 Trigger event upon a rising edge #10 value4 Trigger event upon any edge #11 XTSEL External Trigger Input Selection 8 3 read-write XTWC Write Control for Trigger Configuration 15 write-only value1 No write access to trigger configuration #0 value2 Bitfields XTMODE and XTSEL can be written #1 QINR0 Queue 0 Input Register 0x110 32 read-write n 0x0 0xFFFFFFFF ENSI Enable Source Interrupt 6 write-only value1 No request source interrupt #0 value2 A request source event interrupt is generated upon a request source event (related conversion is finished) #1 EXTR External Trigger 7 write-only value1 A valid queue entry immediately leads to a conversion request. #0 value2 A valid queue entry waits for a trigger event to occur before issuing a conversion request. #1 REQCHNR Request Channel Number 0 4 write-only RF Refill 5 write-only value1 No refill: this queue entry is converted once and then invalidated #0 value2 Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started #1 QMR0 Queue 0 Mode Register 0x104 32 read-write n 0x0 0xFFFFFFFF CEV Clear Event Flag 11 write-only value1 No action #0 value2 Clear bit EV #1 CLRV Clear Valid Bit 8 write-only value1 No action #0 value2 The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared. #1 ENGT Enable Gate 0 1 read-write value1 No conversion requests are issued #00 value2 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register #01 value3 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1 #10 value4 Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0 #11 ENTR Enable External Trigger 2 read-write value1 External trigger disabled #0 value2 The selected edge at the selected trigger input signal REQTR generates the trigger event #1 FLUSH Flush Queue 10 write-only value1 No action #0 value2 Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry. #1 RPTDIS Repeat Disable 16 read-write value1 A cancelled conversion is repeated #0 value2 A cancelled conversion is discarded #1 TREV Trigger Event 9 write-only value1 No action #0 value2 Generate a trigger event by software #1 QSR0 Queue 0 Status Register 0x108 32 read-write n 0x0 0xFFFFFFFF EMPTY Queue Empty 5 read-only value1 There are valid entries in the queue (see FILL) #0 value2 No valid entries (queue is empty) #1 EV Event Detected 8 read-only value1 No trigger event #0 value2 A trigger event has been detected #1 FILL Filling Level for Queue 2 0 3 read-only value1 There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue #0000 value2 There are 2 valid entries in the queue #0001 value3 There are 3 valid entries in the queue #0010 value4 There are 8 valid entries in the queue #0111 REQGT Request Gate Level 7 read-only value1 The gate input is low #0 value2 The gate input is high #1 RCR[0] Result Control Register 0x500 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[10] Result Control Register 0x1EDC 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[11] Result Control Register 0x2188 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[12] Result Control Register 0x2438 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[13] Result Control Register 0x26EC 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[14] Result Control Register 0x29A4 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[15] Result Control Register 0x2C60 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[1] Result Control Register 0x784 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[2] Result Control Register 0xA0C 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[3] Result Control Register 0xC98 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[4] Result Control Register 0xF28 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[5] Result Control Register 0x11BC 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[6] Result Control Register 0x1454 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[7] Result Control Register 0x16F0 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[8] Result Control Register 0x1990 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 RCR[9] Result Control Register 0x1C34 32 read-write n 0x0 0xFFFFFFFF DMM Data Modification Mode 20 1 read-write value1 Standard data reduction (accumulation) #00 value2 Result filtering mode #01 value3 Difference mode #10 DRCTR Data Reduction Control 16 3 read-write FEN FIFO Mode Enable 25 1 read-write value1 Separate result register #00 value2 Part of a FIFO structure: copy each new valid result #01 SRGEN Service Request Generation Enable 31 read-write value1 No service request #0 value2 Service request after a result event #1 WFR Wait-for-Read Mode Enable 24 read-write value1 Overwrite mode #0 value2 Wait-for-read mode enabled for this register #1 REFCLR Result Event Flag Clear Register 0x194 32 read-write n 0x0 0xFFFFFFFF REV0 Clear Result Event for Result Register 0 0 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV1 Clear Result Event for Result Register 1 1 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV10 Clear Result Event for Result Register 10 10 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV11 Clear Result Event for Result Register 11 11 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV12 Clear Result Event for Result Register 12 12 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV13 Clear Result Event for Result Register 13 13 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV14 Clear Result Event for Result Register 14 14 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV15 Clear Result Event for Result Register 15 15 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV2 Clear Result Event for Result Register 2 2 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV3 Clear Result Event for Result Register 3 3 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV4 Clear Result Event for Result Register 4 4 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV5 Clear Result Event for Result Register 5 5 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV6 Clear Result Event for Result Register 6 6 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV7 Clear Result Event for Result Register 7 7 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV8 Clear Result Event for Result Register 8 8 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REV9 Clear Result Event for Result Register 9 9 write-only value1 No action #0 value2 Clear the result event flag in GxREFLAG #1 REFLAG Result Event Flag Register 0x184 32 read-write n 0x0 0xFFFFFFFF REV0 Result Event for Result Register 0 0 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV1 Result Event for Result Register 1 1 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV10 Result Event for Result Register 10 10 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV11 Result Event for Result Register 11 11 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV12 Result Event for Result Register 12 12 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV13 Result Event for Result Register 13 13 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV14 Result Event for Result Register 14 14 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV15 Result Event for Result Register 15 15 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV2 Result Event for Result Register 2 2 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV3 Result Event for Result Register 3 3 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV4 Result Event for Result Register 4 4 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV5 Result Event for Result Register 5 5 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV6 Result Event for Result Register 6 6 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV7 Result Event for Result Register 7 7 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV8 Result Event for Result Register 8 8 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 REV9 Result Event for Result Register 9 9 read-write value1 No result event #0 value2 New result was stored in register GxRESy #1 RESD[0] Result Register, Debug 0x700 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[10] Result Register, Debug 0x2ADC 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[11] Result Register, Debug 0x2E88 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[12] Result Register, Debug 0x3238 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[13] Result Register, Debug 0x35EC 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[14] Result Register, Debug 0x39A4 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[15] Result Register, Debug 0x3D60 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[1] Result Register, Debug 0xA84 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[2] Result Register, Debug 0xE0C 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[3] Result Register, Debug 0x1198 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[4] Result Register, Debug 0x1528 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[5] Result Register, Debug 0x18BC 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[6] Result Register, Debug 0x1C54 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[7] Result Register, Debug 0x1FF0 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[8] Result Register, Debug 0x2390 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RESD[9] Result Register, Debug 0x2734 32 read-write n 0x0 0xFFFFFFFF CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-only VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[0] Result Register 0x600 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[10] Result Register 0x24DC 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[11] Result Register 0x2808 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[12] Result Register 0x2B38 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[13] Result Register 0x2E6C 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[14] Result Register 0x31A4 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[15] Result Register 0x34E0 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[1] Result Register 0x904 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[2] Result Register 0xC0C 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[3] Result Register 0xF18 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[4] Result Register 0x1228 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[5] Result Register 0x153C 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[6] Result Register 0x1854 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[7] Result Register 0x1B70 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[8] Result Register 0x1E90 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 RES[9] Result Register 0x21B4 32 read-write n 0x0 0xFFFFFFFF modifyExternal CHNR Channel Number 20 4 read-only CRS Converted Request Source 28 1 read-only value1 Request source 0 #00 value2 Request source 1 #01 value3 Request source 2 #10 DRC Data Reduction Counter 16 3 read-only EMUX External Multiplexer Setting 25 2 read-only FCR Fast Compare Result 30 read-only value1 Signal level was below compare value #0 value2 Signal level was above compare value #1 RESULT Result of Most Recent Conversion 0 15 read-write VF Valid Flag 31 read-only value1 No new result available #0 value2 Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated #1 REVNP0 Result Event Node Pointer Register 0 0x1B0 32 read-write n 0x0 0xFFFFFFFF REV0NP Service Request Node Pointer Result Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV1NP Service Request Node Pointer Result Event i 4 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV2NP Service Request Node Pointer Result Event i 8 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV3NP Service Request Node Pointer Result Event i 12 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV4NP Service Request Node Pointer Result Event i 16 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV5NP Service Request Node Pointer Result Event i 20 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV6NP Service Request Node Pointer Result Event i 24 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV7NP Service Request Node Pointer Result Event i 28 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REVNP1 Result Event Node Pointer Register 1 0x1B4 32 read-write n 0x0 0xFFFFFFFF REV10NP Service Request Node Pointer Result Event i 8 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV11NP Service Request Node Pointer Result Event i 12 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV12NP Service Request Node Pointer Result Event i 16 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV13NP Service Request Node Pointer Result Event i 20 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV14NP Service Request Node Pointer Result Event i 24 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV15NP Service Request Node Pointer Result Event i 28 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV8NP Service Request Node Pointer Result Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 REV9NP Service Request Node Pointer Result Event i 4 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SEFCLR Source Event Flag Clear Register 0x198 32 read-write n 0x0 0xFFFFFFFF SEV0 Clear Source Event 0/1 0 write-only value1 No action #0 value2 Clear the source event flag in GxSEFLAG #1 SEV1 Clear Source Event 0/1 1 write-only value1 No action #0 value2 Clear the source event flag in GxSEFLAG #1 SEFLAG Source Event Flag Register 0x188 32 read-write n 0x0 0xFFFFFFFF SEV0 Source Event 0/1 0 read-write value1 No source event #0 value2 A source event has occurred #1 SEV1 Source Event 0/1 1 read-write value1 No source event #0 value2 A source event has occurred #1 SEVNP Source Event Node Pointer Register 0x1C0 32 read-write n 0x0 0xFFFFFFFF SEV0NP Service Request Node Pointer Source Event i 0 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SEV1NP Service Request Node Pointer Source Event i 4 3 read-write value1 Select service request line 0 of group x #0000 value2 Select service request line 3 of group x #0011 value3 Select shared service request line 0 #0100 value4 Select shared service request line 3 #0111 SRACT Service Request Software Activation Trigger 0x1C8 32 read-write n 0x0 0xFFFFFFFF AGSR0 Activate Group Service Request Node 0 0 write-only value1 No action #0 value2 Activate the associated service request line #1 AGSR1 Activate Group Service Request Node 1 1 write-only value1 No action #0 value2 Activate the associated service request line #1 AGSR2 Activate Group Service Request Node 2 2 write-only value1 No action #0 value2 Activate the associated service request line #1 AGSR3 Activate Group Service Request Node 3 3 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR0 Activate Shared Service Request Node 0 8 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR1 Activate Shared Service Request Node 1 9 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR2 Activate Shared Service Request Node 2 10 write-only value1 No action #0 value2 Activate the associated service request line #1 ASSR3 Activate Shared Service Request Node 3 11 write-only value1 No action #0 value2 Activate the associated service request line #1 SYNCTR Synchronization Control Register 0xC0 32 read-write n 0x0 0xFFFFFFFF EVALR1 Evaluate Ready Input Rx 4 read-write value1 No ready input control #0 value2 Ready input Rx is considered for the start of a parallel conversion of this conversion group #1 EVALR2 Evaluate Ready Input Rx 5 read-write value1 No ready input control #0 value2 Ready input Rx is considered for the start of a parallel conversion of this conversion group #1 EVALR3 Evaluate Ready Input Rx 6 read-write value1 No ready input control #0 value2 Ready input Rx is considered for the start of a parallel conversion of this conversion group #1 STSEL Start Selection 0 1 read-write value1 Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC #00 value2 Kernel is synchronization slave: Control information from input CI1 #01 value3 Kernel is synchronization slave: Control information from input CI2 #10 value4 Kernel is synchronization slave: Control information from input CI3 #11 VFR Valid Flag Register 0x1F8 32 read-write n 0x0 0xFFFFFFFF VF0 Valid Flag of Result Register x 0 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF1 Valid Flag of Result Register x 1 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF10 Valid Flag of Result Register x 10 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF11 Valid Flag of Result Register x 11 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF12 Valid Flag of Result Register x 12 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF13 Valid Flag of Result Register x 13 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF14 Valid Flag of Result Register x 14 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF15 Valid Flag of Result Register x 15 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF2 Valid Flag of Result Register x 2 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF3 Valid Flag of Result Register x 3 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF4 Valid Flag of Result Register x 4 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF5 Valid Flag of Result Register x 5 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF6 Valid Flag of Result Register x 6 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF7 Valid Flag of Result Register x 7 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF8 Valid Flag of Result Register x 8 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 VF9 Valid Flag of Result Register x 9 read-write value1 Read access: No new valid data available Write access: No effect #0 value2 Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action) #1 UART0 UART 0 UART 0x41303000 0x0 0x14 registers n UART0_TX UART 0 TX 33 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART0_Secure UART 0 (Secure) UART 0x51303000 0x0 0x14 registers n BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART1 UART 1 UART 0x41304000 0x0 0x14 registers n UART1_TX UART 1 TX 35 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART1_Secure UART 1 (Secure) CCU4 0x51304000 0x0 0x100 registers n C0V Capture Register 0 0x74 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C1V Capture Register 1 0x78 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C2V Capture Register 2 0x7C 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C3V Capture Register 3 0x80 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only CMC Connection Matrix Control 0x4 32 read-write n 0x0 0xFFFFFFFF CAP0S External Capture 0 Functionality Selector 4 1 read-write value1 External Capture 0 Function deactivated #00 value2 External Capture 0 Function triggered by Event 0 #01 value3 External Capture 0 Function triggered by Event 1 #10 value4 External Capture 0 Function triggered by Event 2 #11 CAP1S External Capture 1 Functionality Selector 6 1 read-write value1 External Capture 1 Function deactivated #00 value2 External Capture 1 Function triggered by Event 0 #01 value3 External Capture 1 Function triggered by Event 1 #10 value4 External Capture 1 Function triggered by Event 2 #11 CNTS External Count Selector 14 1 read-write value1 External Count Function deactivated #00 value2 External Count Function triggered by Event 0 #01 value3 External Count Function triggered by Event 1 #10 value4 External Count Function triggered by Event 2 #11 ENDS External Stop Functionality Selector 2 1 read-write value1 External Stop Function deactivated #00 value2 External Stop Function triggered by Event 0 #01 value3 External Stop Function triggered by Event 1 #10 value4 External Stop Function triggered by Event 2 #11 GATES External Gate Functionality Selector 8 1 read-write value1 External Gating Function deactivated #00 value2 External Gating Function triggered by Event 0 #01 value3 External Gating Function triggered by Event 1 #10 value4 External Gating Function triggered by Event 2 #11 LDS External Timer Load Functionality Selector 12 1 read-write MOS External Modulation Functionality Selector 18 1 read-write OFS Override Function Selector 16 read-write value1 Override functionality disabled #0 value2 Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 #1 STRTS External Start Functionality Selector 0 1 read-write value1 External Start Function deactivated #00 value2 External Start Function triggered by Event 0 #01 value3 External Start Function triggered by Event 1 #10 value4 External Start Function triggered by Event 2 #11 TCE Timer Concatenation Enable 20 read-write value1 Timer concatenation is disabled #0 value2 Timer concatenation is enabled #1 TS Trap Function Selector 17 read-write value1 Trap function disabled #0 value2 TRAP function connected to Event 2 #1 UDS External Up/Down Functionality Selector 10 1 read-write value1 External Up/Down Function deactivated #00 value2 External Up/Down Function triggered by Event 0 #01 value3 External Up/Down Function triggered by Event 1 #10 value4 External Up/Down Function triggered by Event 2 #11 CR Timer Compare Value 0x38 32 read-write n 0x0 0xFFFFFFFF CR Compare Register 0 15 read-only CRS Timer Shadow Compare Value 0x3C 32 read-write n 0x0 0xFFFFFFFF CRS Compare Register 0 15 read-write DIT Dither Config 0x1C 32 read-write n 0x0 0xFFFFFFFF DCNT Dither counter actual value 8 3 read-only DCV Dither compare Value 0 3 read-only DITS Dither Shadow Register 0x20 32 read-write n 0x0 0xFFFFFFFF DCVS Dither Shadow Compare Value 0 3 read-write FPC Floating Prescaler Control 0x28 32 read-write n 0x0 0xFFFFFFFF PCMP Floating Prescaler Compare Value 0 3 read-only PVAL Actual Prescaler Value 8 3 read-write FPCS Floating Prescaler Shadow 0x2C 32 read-write n 0x0 0xFFFFFFFF PCMP Floating Prescaler Shadow Compare Value 0 3 read-write INS Input Selector Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF EV0EM Event 0 Edge Selection 16 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV0IS Event 0 signal selection 0 3 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV0LM Event 0 Level Selection 22 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV1EM Event 1 Edge Selection 18 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV1IS Event 1 signal selection 4 3 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV1LM Event 1 Level Selection 23 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV2EM Event 2 Edge Selection 20 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV2IS Event 2 signal selection 8 3 read-write value1 CCU4x.INyA #0000 value2 CCU4x.INyB #0001 value3 CCU4x.INyC #0010 value4 CCU4x.INyD #0011 value5 CCU4x.INyE #0100 value6 CCU4x.INyF #0101 value7 CCU4x.INyG #0110 value8 CCU4x.INyH #0111 value9 CCU4x.INyI #1000 value10 CCU4x.INyJ #1001 value11 CCU4x.INyK #1010 value12 CCU4x.INyL #1011 value13 CCU4x.INyM #1100 value14 CCU4x.INyN #1101 value15 CCU4x.INyO #1110 value16 CCU4x.INyP #1111 EV2LM Event 2 Level Selection 24 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 LPF0M Event 0 Low Pass Filter Configuration 25 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 LPF1M Event 1 Low Pass Filter Configuration 27 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 LPF2M Event 2 Low Pass Filter Configuration 29 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU4 #01 value3 5 clock cycles of fCCU4 #10 value4 7 clock cycles of fCCU4 #11 INTE Interrupt Enable Control 0xA4 32 read-write n 0x0 0xFFFFFFFF CMDE Compare match while counting down enable 3 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 CMUE Compare match while counting up enable 2 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 E0AE Event 0 interrupt enable 8 read-write value1 Event 0 detection interrupt is disabled #0 value2 Event 0 detection interrupt is enabled #1 E1AE Event 1 interrupt enable 9 read-write value1 Event 1 detection interrupt is disabled #0 value2 Event 1 detection interrupt is enabled #1 E2AE Event 2 interrupt enable 10 read-write value1 Event 2 detection interrupt is disabled #0 value2 Event 2 detection interrupt is enabled #1 OME One match while counting down enable 1 read-write value1 One Match interrupt is disabled #0 value2 One Match interrupt is enabled #1 PME Period match while counting up enable 0 read-write value1 Period Match interrupt is disabled #0 value2 Period Match interrupt is enabled #1 INTS Interrupt Status 0xA0 32 read-write n 0x0 0xFFFFFFFF CMDS Compare Match while Counting Down 3 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 CMUS Compare Match while Counting Up 2 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 E0AS Event 0 Detection Status 8 read-only value1 Event 0 not detected #0 value2 Event 0 detected #1 E1AS Event 1 Detection Status 9 read-only value1 Event 1 not detected #0 value2 Event 1 detected #1 E2AS Event 2 Detection Status 10 read-only value1 Event 2 not detected #0 value2 Event 2 detected #1 OMDS One Match while Counting Down 1 read-only value1 One match while counting down not detected #0 value2 One match while counting down detected #1 PMUS Period Match while Counting Up 0 read-only value1 Period match while counting up not detected #0 value2 Period match while counting up detected #1 TRPF Trap Flag Status 11 read-only PR Timer Period Value 0x30 32 read-write n 0x0 0xFFFFFFFF PR Period Register 0 15 read-only PRS Timer Shadow Period Value 0x34 32 read-write n 0x0 0xFFFFFFFF PRS Period Register 0 15 read-write PSC Prescaler Control 0x24 32 read-write n 0x0 0xFFFFFFFF PSIV Prescaler Initial Value 0 3 read-write PSL Passive Level Config 0x18 32 read-write n 0x0 0xFFFFFFFF PSL Output Passive Level 0 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 SRS Service Request Selector 0xA8 32 read-write n 0x0 0xFFFFFFFF CMSR Compare match Service request selector 2 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E0SR Event 0 Service request selector 8 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E1SR Event 1 Service request selector 10 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 E2SR Event 2 Service request selector 12 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 POSR Period/One match Service request selector 0 1 read-write value1 Forward to CC4ySR0 #00 value2 Forward to CC4ySR1 #01 value3 Forward to CC4ySR2 #10 value4 Forward to CC4ySR3 #11 SWR Interrupt Status Clear 0xB0 32 read-write n 0x0 0xFFFFFFFF RCMD Compare match while counting down clear 3 write-only RCMU Compare match while counting up clear 2 write-only RE0A Event 0 detection clear 8 write-only RE1A Event 1 detection clear 9 write-only RE2A Event 2 detection clear 10 write-only ROM One match while counting down clear 1 write-only RPM Period match while counting up clear 0 write-only RTRPF Trap Flag status clear 11 write-only SWS Interrupt Status Set 0xAC 32 read-write n 0x0 0xFFFFFFFF SCMD Compare match while counting down set 3 write-only SCMU Compare match while counting up set 2 write-only SE0A Event 0 detection set 8 write-only SE1A Event 1 detection set 9 write-only SE2A Event 2 detection set 10 write-only SOM One match while counting down set 1 write-only SPM Period match while counting up set 0 write-only STRPF Trap Flag status set 11 write-only TC Slice Timer Control 0x14 32 read-write n 0x0 0xFFFFFFFF CAPC Clear on Capture Control 5 1 read-write value1 Timer is never cleared on a capture event #00 value2 Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) #01 value3 Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) #10 value4 Timer is always cleared in a capture event. #11 CCS Continuous Capture Enable 12 read-write value1 The capture into a specific capture register is done with the rules linked with the full flags, described at . #0 value2 The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). #1 CLST Shadow Transfer on Clear 2 read-write CMOD Capture Compare Mode 3 read-only value1 Compare Mode #0 value2 Capture Mode #1 DIM Dither input selector 15 read-write value1 Slice is using its own dither unit #0 value2 Slice is connected to the dither unit of slice 0. #1 DITHE Dither Enable 13 1 read-write value1 Dither is disabled #00 value2 Dither is applied to the Period #01 value3 Dither is applied to the Compare #10 value4 Dither is applied to the Period and Compare #11 ECM Extended Capture Mode 4 read-write value1 Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. #0 value2 Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the ECRD.VPTR is cleared. #1 EMS External Modulation Synchronization 23 read-write value1 External Modulation functionality is not synchronized with the PWM signal #0 value2 External Modulation functionality is synchronized with the PWM signal #1 EMT External Modulation Type 24 read-write value1 External Modulation functionality is clearing the CC4yST bit. #0 value2 External Modulation functionality is gating the outputs. #1 ENDM Extended Stop Function Control 8 1 read-write value1 Clears the timer run bit only (default stop) #00 value2 Clears the timer only (flush) #01 value3 Clears the timer and run bit (flush/stop) #10 FPE Floating Prescaler enable 16 read-write value1 Floating prescaler mode is disabled #0 value2 Floating prescaler mode is enabled #1 MCME Multi Channel Mode Enable 25 read-write value1 Multi Channel Mode is disabled #0 value2 Multi Channel Mode is enabled #1 SCE Equal Capture Event enable 11 read-write value1 Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #0 value2 Capture into CC4yC0VThis register contains the values associated with the Capture 0 field./CC4yC1VThis register contains the values associated with the Capture 1 field. and CC4yC3VThis register contains the values associated with the Capture 3 field./CC4yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #1 STRM Extended Start Function Control 10 read-write value1 Sets run bit only (default start) #0 value2 Clears the timer and sets run bit (flush/start) #1 TCM Timer Counting Mode 0 read-write value1 Edge aligned mode #0 value2 Center aligned mode #1 TRAPE TRAP enable 17 read-write value1 TRAP functionality has no effect on the output #0 value2 TRAP functionality affects the output #1 TRPSE TRAP Synchronization Enable 21 read-write value1 Exiting from TRAP state isn't synchronized with the PWM signal #0 value2 Exiting from TRAP state is synchronized with the PWM signal #1 TRPSW TRAP State Clear Control 22 read-write value1 The slice exits the TRAP state automatically when the TRAP condition is not present #0 value2 The TRAP state can only be exited by a SW request. #1 TSSM Timer Single Shot Mode 1 read-write value1 Single shot mode is disabled #0 value2 Single shot mode is enabled #1 TCCLR Slice Timer Clear 0x10 32 read-write n 0x0 0xFFFFFFFF DITC Dither Counter Clear 2 write-only TCC Timer Clear 1 write-only TRBC Timer Run Bit Clear 0 write-only TCSET Slice Timer Run Set 0xC 32 read-write n 0x0 0xFFFFFFFF TRBS Timer Run Bit set 0 write-only TCST Slice Timer Status 0x8 32 read-write n 0x0 0xFFFFFFFF CDIR Timer Counting Direction 1 read-only value1 Timer is counting up #0 value2 Timer is counting down #1 TRB Timer Run Bit 0 read-only value1 Timer is stopped #0 value2 Timer is running #1 TIMER Timer Value 0x70 32 read-write n 0x0 0xFFFFFFFF TVAL Timer Value 0 15 read-write UART2 UART 2 UART 0x41305000 0x0 0x14 registers n UART2_TX UART 2 TX 37 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART2_Secure UART 2 (Secure) CCU8 0x51305000 0x0 0x100 registers n ECRD Extended Capture Mode Read 0x50 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPV Timer Capture Value 0 15 read-only FFL Full Flag 24 read-only value1 No new value was captured into this register #0 value2 A new value has been captured into this register #1 FPCV Prescaler Capture value 16 3 read-only SPTR Slice pointer 20 1 read-only value1 CC80 #00 value2 CC81 #01 value3 CC82 #10 value4 CC83 #11 VPTR Capture register pointer 22 1 read-only value1 Capture register 0 #00 value2 Capture register 1 #01 value3 Capture register 2 #10 value4 Capture register 3 #11 GCSC Global Channel Clear 0x14 32 read-write n 0x0 0xFFFFFFFF S0DSC Slice 0 Dither shadow transfer clear 1 write-only S0PSC Slice 0 Prescaler shadow transfer clear 2 write-only S0SC Slice 0 shadow transfer request clear 0 write-only S0ST1C Slice 0 status bit 1 clear 16 write-only S0ST2C Slice 0 status bit 2 clear 20 write-only S1DSC Slice 1 Dither shadow transfer clear 5 write-only S1PSC Slice 1 Prescaler shadow transfer clear 6 write-only S1SC Slice 1 shadow transfer clear 4 write-only S1ST1C Slice 1 status bit 1 clear 17 write-only S1ST2C Slice 1 status bit 2 clear 21 write-only S2DSC Slice 2 Dither shadow transfer clear 9 write-only S2PSC Slice 2 Prescaler shadow transfer clear 10 write-only S2SC Slice 2 shadow transfer clear 8 write-only S2ST1C Slice 2 status bit 1 clear 18 write-only S2ST2C Slice 2 status bit 2 clear 22 write-only S3DSC Slice 3 Dither shadow transfer clear 13 write-only S3PSC Slice 3 Prescaler shadow transfer clear 14 write-only S3SC Slice 3 shadow transfer clear 12 write-only S3ST1C Slice 3 status bit 1 clear 19 write-only S3ST2C Slice 3 status bit 2 clear 23 write-only GCSS Global Channel Set 0x10 32 read-write n 0x0 0xFFFFFFFF S0DSE Slice 0 Dither shadow transfer set enable 1 write-only S0PSE Slice 0 Prescaler shadow transfer set enable 2 write-only S0SE Slice 0 shadow transfer set enable 0 write-only S0ST1S Slice 0 status bit 1 set 16 write-only S0ST2S Slice 0 status bit 2 set 20 write-only S1DSE Slice 1 Dither shadow transfer set enable 5 write-only S1PSE Slice 1 Prescaler shadow transfer set enable 6 write-only S1SE Slice 1 shadow transfer set enable 4 write-only S1ST1S Slice 1 status bit 1 set 17 write-only S1ST2S Slice 1 status bit 2 set 21 write-only S2DSE Slice 2 Dither shadow transfer set enable 9 write-only S2PSE Slice 2 Prescaler shadow transfer set enable 10 write-only S2SE Slice 2 shadow transfer set enable 8 write-only S2ST1S Slice 2 status bit 1 set 18 write-only S2ST2S Slice 2 status bit 2 set 22 write-only S3DSE Slice 3 Dither shadow transfer set enable 13 write-only S3PSE Slice 3 Prescaler shadow transfer set enable 14 write-only S3SE Slice 3 shadow transfer set enable 12 write-only S3ST1S Slice 3 status bit 1 set 19 write-only S3ST2S Slice 3 status bit 2 set 23 write-only GCST Global Channel status 0x18 32 read-write n 0x0 0xFFFFFFFF CC80ST1 Slice 0 compare channel 1 status bit 16 read-only CC80ST2 Slice 0 compare channel 2 status bit 20 read-only CC81ST1 Slice 1 compare channel 1 status bit 17 read-only CC81ST2 Slice 1 compare channel 2 status bit 21 read-only CC82ST1 Slice 2 compare channel 1 status bit 18 read-only CC82ST2 Slice 2 compare channel 2 status bit 22 read-only CC83ST1 Slice 3 compare channel 1 status bit 19 read-only CC83ST2 Slice 3 compare channel 2 status bit 23 read-only S0DSS Slice 0 Dither shadow transfer status 1 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S0PSS Slice 0 Prescaler shadow transfer status 2 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S0SS Slice 0 shadow transfer status 0 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S1DSS Slice 1 Dither shadow transfer status 5 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S1PSS Slice 1 Prescaler shadow transfer status 6 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S1SS Slice 1 shadow transfer status 4 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S2DSS Slice 2 Dither shadow transfer status 9 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S2PSS Slice 2 Prescaler shadow transfer status 10 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S2SS Slice 2 shadow transfer status 8 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 S3DSS Slice 3 Dither shadow transfer status 13 read-only value1 Dither shadow transfer has not been requested #0 value2 Dither shadow transfer has been requested #1 S3PSS Slice 3 Prescaler shadow transfer status 14 read-only value1 Prescaler shadow transfer has not been requested #0 value2 Prescaler shadow transfer has been requested #1 S3SS Slice 3 shadow transfer status 12 read-only value1 Shadow transfer has not been requested #0 value2 Shadow transfer has been requested #1 GCTRL Global Control Register 0x0 32 read-write n 0x0 0xFFFFFFFF MSDE Multi Channel shadow transfer request configuration 14 1 read-write value1 Only the shadow transfer for period and compare values is requested #00 value2 Shadow transfer for the compare, period and prescaler compare values is requested #01 value4 Shadow transfer for the compare, period, prescaler and dither compare values is requested #11 MSE0 Slice 0 Multi Channel shadow transfer enable 10 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 MSE1 Slice 1 Multi Channel shadow transfer enable 11 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 MSE2 Slice 2 Multi Channel shadow transfer enable 12 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8xMCSS input. #1 MSE3 Slice 3 Multi Channel shadow transfer enable 13 read-write value1 Shadow transfer can only be requested by SW #0 value2 Shadow transfer can be requested via SW and via the CCU8x.MCSS input. #1 PCIS Prescaler Input Clock Selection 4 1 read-write value1 Module clock #00 value2 CCU8x.ECLKA #01 value3 CCU8x.ECLKB #10 value4 CCU8x.ECLKC #11 PRBC Prescaler Clear Configuration 0 2 read-write value1 SW only #000 value2 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC80 is cleared. #001 value3 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC81 is cleared. #010 value4 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC82 is cleared. #011 value5 GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC83 is cleared. #100 SUSCFG Suspend Mode Configuration 8 1 read-write value1 Suspend request ignored. The module never enters in suspend #00 value2 Stops all the running slices immediately. Safe stop is not applied. #01 value3 Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied. #10 value4 Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied. #11 GIDLC Global Idle Clear 0xC 32 read-write n 0x0 0xFFFFFFFF CS0I CC80 IDLE mode clear 0 write-only CS1I CC81 IDLE mode clear 1 write-only CS2I CC82 IDLE mode clear 2 write-only CS3I CC83 IDLE mode clear 3 write-only SPCH Parity Checker run bit set 10 write-only SPRB Prescaler Run Bit Set 8 write-only GIDLS Global Idle Set 0x8 32 read-write n 0x0 0xFFFFFFFF CPCH Parity Checker Run bit clear 10 write-only CPRB Prescaler# Run Bit Clear 8 write-only PSIC Prescaler clear 9 write-only SS0I CC80 IDLE mode set 0 write-only SS1I CC81 IDLE mode set 1 write-only SS2I CC82 IDLE mode set 2 write-only SS3I CC83 IDLE mode set 3 write-only GPCHK Parity Checker Configuration 0x1C 32 read-write n 0x0 0xFFFFFFFF PACS Parity Checker Automatic start/stop selector 1 1 read-write value1 CC80 #00 value2 CC81 #01 value3 CC82 #10 value4 CC83 #11 PASE Parity Checker Automatic start/stop 0 read-write PCDS Parity Checker Delay Input Selector 5 1 read-write value1 CCU8x.IGBTA #00 value2 CCU8x.IGBTB #01 value3 CCU8x.IGBTC #10 value4 CCU8x.IGBTD #11 PCSEL0 Parity Checker Slice 0 output selection 16 3 read-write PCSEL1 Parity Checker Slice 1 output selection 20 3 read-write PCSEL2 Parity Checker Slice 2 output selection 24 3 read-write PCSEL3 Parity Checker Slice 3 output selection 28 3 read-write PCST Parity Checker XOR status 15 read-only PCTS Parity Checker type selector 7 read-write value1 Even parity enabled #0 value2 Odd parity enabled #1 PISEL Driver Input signal selector 3 1 read-write value1 CC8x.GP01 - driver output is connected to event 1 of slice 0 #00 value2 CC8x.GP11 - drive output is connected to event 1 of slice 1 #01 value3 CC8x.GP21 - driver output is connected to event 1 of slice 2 #10 value4 CC8x.GP31 - driver output is connected to event 1 of slice 3 #11 GSTAT Global Status Register 0x4 32 read-write n 0x0 0xFFFFFFFF PCRB Parity Checker Run Bit 10 read-only value1 Parity Checker is stopped #0 value2 Parity Checker is running #1 PRB Prescaler Run Bit 8 read-only value1 Prescaler is stopped #0 value2 Prescaler is running #1 S0I CC80 IDLE status 0 read-only value1 Running #0 value2 Idle #1 S1I CC81 IDLE status 1 read-only value1 Running #0 value2 Idle #1 S2I CC82 IDLE status 2 read-only value1 Running #0 value2 Idle #1 S3I CC83 IDLE status 3 read-only value1 Running #0 value2 Idle #1 MIDR Module Identification 0x80 32 read-write n 0x0 0xFFFFFF00 MODN Module Number 16 15 read-only MODR Module Revision 0 7 read-only MODT Module Type 8 7 read-only UART3 UART 3 UART 0x41306000 0x0 0x14 registers n UART3_TX UART 3 TX 39 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART3_Secure UART 3 (Secure) CCU8 0x51306000 0x0 0x100 registers n C0V Capture Register 0 0x74 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C1V Capture Register 1 0x78 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C2V Capture Register 2 0x7C 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only C3V Capture Register 3 0x80 32 read-write n 0x0 0xFFFFFFFF modifyExternal CAPTV Capture Value 0 15 read-only FFL Full Flag 20 read-only value1 No new value was captured into the specific capture register #0 value2 A new value was captured into the specific register #1 FPCV Prescaler Value 16 3 read-only CHC Channel Control 0x48 32 read-write n 0x0 0xFFFFFFFF ASE Asymmetric PWM mode Enable 0 read-write value1 Asymmetric PWM is disabled #0 value2 Asymmetric PWM is enabled #1 OCS1 Output selector for CCU8x.OUTy0 1 read-write value1 CC8yST1 signal path is connected to the CCU8x.OUTy0 #0 value2 Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0 #1 OCS2 Output selector for CCU8x.OUTy1 2 read-write value1 Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1 #0 value2 CC8yST1 signal path is connected to the CCU8x.OUTy1 #1 OCS3 Output selector for CCU8x.OUTy2 3 read-write value1 CC8yST2 signal path is connected to the CCU8x.OUTy2 #0 value2 Inverted CCST2 signal path is connected to the CCU8x.OUTy2 #1 OCS4 Output selector for CCU8x.OUTy3 4 read-write value1 Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3 #0 value2 CC8yST2 signal path is connected to the CCU8x.OUTy3 #1 CMC Connection Matrix Control 0x4 32 read-write n 0x0 0xFFFFFFFF CAP0S External Capture 0 Functionality Selector 4 1 read-write value1 External Capture 0 Function deactivated #00 value2 External Capture 0 Function triggered by Event 0 #01 value3 External Capture 0 Function triggered by Event 1 #10 value4 External Capture 0 Function triggered by Event 2 #11 CAP1S External Capture 1 Functionality Selector 6 1 read-write value1 External Capture 1 Function deactivated #00 value2 External Capture 1 Function triggered by Event 0 #01 value3 External Capture 1 Function triggered by Event 1 #10 value4 External Capture 1 Function triggered by Event 2 #11 CNTS External Count Selector 14 1 read-write value1 External Count Function deactivated #00 value2 External Count Function triggered by Event 0 #01 value3 External Count Function triggered by Event 1 #10 value4 External Count Function triggered by Event 2 #11 ENDS External Stop Functionality Selector 2 1 read-write value1 External Stop Function deactivated #00 value2 External Stop Function triggered by Event 0 #01 value3 External Stop Function triggered by Event 1 #10 value4 External Stop Function triggered by Event 2 #11 GATES External Gate Functionality Selector 8 1 read-write value1 External Gating Function deactivated #00 value2 External Gating Function triggered by Event 0 #01 value3 External Gating Function triggered by Event 1 #10 value4 External Gating Function triggered by Event 2 #11 LDS External Timer Load Functionality Selector 12 1 read-write MOS External Modulation Functionality Selector 18 1 read-write OFS Override Function Selector 16 read-write value1 Override functionality disabled #0 value2 Status bit trigger override connected to Event 1; Status bit value override connected to Event 2 #1 STRTS External Start Functionality Selector 0 1 read-write value1 External Start Function deactivated #00 value2 External Start Function triggered by Event 0 #01 value3 External Start Function triggered by Event 1 #10 value4 External Start Function triggered by Event 2 #11 TCE Timer Concatenation Enable 20 read-write value1 Timer concatenation is disabled #0 value2 Timer concatenation is enabled #1 TS Trap Function Selector 17 read-write value1 Trap function disabled #0 value2 TRAP function connected to Event 2 #1 UDS External Up/Down Functionality Selector 10 1 read-write value1 External Up/Down Function deactivated #00 value2 External Up/Down Function triggered by Event 0 #01 value3 External Up/Down Function triggered by Event 1 #10 value4 External Up/Down Function triggered by Event 2 #11 CR1 Channel 1 Compare Value 0x38 32 read-write n 0x0 0xFFFFFFFF CR1 Compare Register for Channel 1 0 15 read-only CR1S Channel 1 Compare Shadow Value 0x3C 32 read-write n 0x0 0xFFFFFFFF CR1S Shadow Compare Register for Channel 1 0 15 read-write CR2 Channel 2 Compare Value 0x40 32 read-write n 0x0 0xFFFFFFFF CR2 Compare Register for Channel 2 0 15 read-only CR2S Channel 2 Compare Shadow Value 0x44 32 read-write n 0x0 0xFFFFFFFF CR2S Shadow Compare Register for Channel 2 0 15 read-write DC1R Channel 1 Dead Time Values 0x50 32 read-write n 0x0 0xFFFFFFFF DT1F Fall Value for Dead Time of Channel 1 8 7 read-write DT1R Rise Value for Dead Time of Channel 1 0 7 read-write DC2R Channel 2 Dead Time Values 0x54 32 read-write n 0x0 0xFFFFFFFF DT2F Fall Value for Dead Time of Channel 2 8 7 read-write DT2R Rise Value for Dead Time of Channel 2 0 7 read-write DIT Dither Config 0x1C 32 read-write n 0x0 0xFFFFFFFF DCNT Dither counter actual value 8 3 read-only DCV Dither compare Value 0 3 read-only DITS Dither Shadow Register 0x20 32 read-write n 0x0 0xFFFFFFFF DCVS Dither Shadow Compare Value 0 3 read-write DTC Dead Time Control 0x4C 32 read-write n 0x0 0xFFFFFFFF DCEN1 Dead Time Enable for CC8yST1 2 read-write value1 Dead Time for CC8yST1 path is disabled #0 value2 Dead Time for CC8yST1 path is enabled #1 DCEN2 Dead Time Enable for inverted CC8yST1 3 read-write value1 Dead Time for inverted CC8yST1 path is disabled #0 value2 Dead Time for inverted CC8yST1 path is enabled #1 DCEN3 Dead Time Enable for CC8yST2 4 read-write value1 Dead Time for CC8yST2 path is disabled #0 value2 Dead Time for CC8yST2 path is enabled #1 DCEN4 Dead Time Enable for inverted CC8yST2 5 read-write value1 Dead Time for inverted CC8yST2 path is disabled #0 value2 Dead Time for inverted CC8yST2 path is enabled #1 DTCC Dead Time clock control 6 1 read-write value1 ftclk #00 value2 ftclk/2 #01 value3 ftclk/4 #10 value4 ftclk/8 #11 DTE1 Dead Time Enable for Channel 1 0 read-write value1 Dead Time for channel 1 is disabled #0 value2 Dead Time for channel 1 is enabled #1 DTE2 Dead Time Enable for Channel 2 1 read-write value1 Dead Time for channel 2 is disabled #0 value2 Dead Time for channel 2 is enabled #1 FPC Floating Prescaler Control 0x28 32 read-write n 0x0 0xFFFFFFFF PCMP Floating Prescaler Compare Value 0 3 read-only PVAL Actual Prescaler Value 8 3 read-write FPCS Floating Prescaler Shadow 0x2C 32 read-write n 0x0 0xFFFFFFFF PCMP Floating Prescaler Shadow Compare Value 0 3 read-write INS Input Selector Configuration 0x0 32 read-write n 0x0 0xFFFFFFFF EV0EM Event 0 Edge Selection 16 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV0IS Event 0 signal selection 0 3 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV0LM Event 0 Level Selection 22 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV1EM Event 1 Edge Selection 18 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV1IS Event 1 signal selection 4 3 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV1LM Event 1 Level Selection 23 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 EV2EM Event 2 Edge Selection 20 1 read-write value1 No action #00 value2 Signal active on rising edge #01 value3 Signal active on falling edge #10 value4 Signal active on both edges #11 EV2IS Event 2 signal selection 8 3 read-write value1 CCU8x.INyA #0000 value2 CCU8x.INyB #0001 value3 CCU8x.INyC #0010 value4 CCU8x.INyD #0011 value5 CCU8x.INyE #0100 value6 CCU8x.INyF #0101 value7 CCU8x.INyG #0110 value8 CCU8x.INyH #0111 value9 CCU8x.INyI #1000 value10 CCU8x.INyJ #1001 value11 CCU8x.INyK #1010 value12 CCU8x.INyL #1011 value13 CCU8x.INyM #1100 value14 CCU8x.INyN #1101 value15 CCU8x.INyO #1110 value16 CCU8x.INyP #1111 EV2LM Event 2 Level Selection 24 read-write value1 Active on HIGH level #0 value2 Active on LOW level #1 LPF0M Event 0 Low Pass Filter Configuration 25 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 LPF1M Event 1 Low Pass Filter Configuration 27 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 LPF2M Event 2 Low Pass Filter Configuration 29 1 read-write value1 LPF is disabled #00 value2 3 clock cycles of fCCU8 #01 value3 5 clock cycles of fCCU8 #10 value4 7 clock cycles of fCCU8 #11 INTE Interrupt Enable Control 0xA4 32 read-write n 0x0 0xFFFFFFFF CMD1E Channel 1 Compare match while counting down enable 3 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 CMD2E Channel 2 Compare match while counting down enable 5 read-write value1 Compare Match while counting down interrupt is disabled #0 value2 Compare Match while counting down interrupt is enabled #1 CMU1E Channel 1 Compare match while counting up enable 2 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 CMU2E Channel 2 Compare match while counting up enable 4 read-write value1 Compare Match while counting up interrupt is disabled #0 value2 Compare Match while counting up interrupt is enabled #1 E0AE Event 0 interrupt enable 8 read-write value1 Event 0 detection interrupt is disabled #0 value2 Event 0 detection interrupt is enabled #1 E1AE Event 1 interrupt enable 9 read-write value1 Event 1 detection interrupt is disabled #0 value2 Event 1 detection interrupt is enabled #1 E2AE Event 2 interrupt enable 10 read-write value1 Event 2 detection interrupt is disabled #0 value2 Event 2 detection interrupt is enabled #1 OME One match while counting down enable 1 read-write value1 One Match interrupt is disabled #0 value2 One Match interrupt is enabled #1 PME Period match while counting up enable 0 read-write value1 Period Match interrupt is disabled #0 value2 Period Match interrupt is enabled #1 INTS Interrupt Status 0xA0 32 read-write n 0x0 0xFFFFFFFF CMD1S Channel 1 Compare Match while Counting Down 3 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 CMD2S Channel 2 Compare Match while Counting Down 5 read-only value1 Compare match while counting down not detected #0 value2 Compare match while counting down detected #1 CMU1S Channel 1 Compare Match while Counting Up 2 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 CMU2S Channel 2 Compare Match while Counting Up 4 read-only value1 Compare match while counting up not detected #0 value2 Compare match while counting up detected #1 E0AS Event 0 Detection Status 8 read-only value1 Event 0 not detected #0 value2 Event 0 detected #1 E1AS Event 1 Detection Status 9 read-only value1 Event 1 not detected #0 value2 Event 1 detected #1 E2AS Event 2 Detection Status 10 read-only value1 Event 2 not detected #0 value2 Event 2 detected #1 OMDS One Match while Counting Down 1 read-only value1 One match while counting down not detected #0 value2 One match while counting down detected #1 PMUS Period Match while Counting Up 0 read-only value1 Period match while counting up not detected #0 value2 Period match while counting up detected #1 TRPF Trap Flag Status 11 read-only PR Timer Period Value 0x30 32 read-write n 0x0 0xFFFFFFFF PR Period Register 0 15 read-only PRS Timer Shadow Period Value 0x34 32 read-write n 0x0 0xFFFFFFFF PRS Period Register 0 15 read-write PSC Prescaler Control 0x24 32 read-write n 0x0 0xFFFFFFFF PSIV Prescaler Initial Value 0 3 read-write PSL Passive Level Config 0x18 32 read-write n 0x0 0xFFFFFFFF PSL11 Output Passive Level for CCU8x.OUTy0 0 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL12 Output Passive Level for CCU8x.OUTy1 1 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL21 Output Passive Level for CCU8x.OUTy2 2 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 PSL22 Output Passive Level for CCU8x.OUTy3 3 read-write value1 Passive Level is LOW #0 value2 Passive Level is HIGH #1 SRS Service Request Selector 0xA8 32 read-write n 0x0 0xFFFFFFFF CM1SR Channel 1 Compare match Service request selector 2 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 CM2SR Channel 2 Compare match Service request selector 4 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E0SR Event 0 Service request selector 8 1 read-write value1 Forward to CCvySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E1SR Event 1 Service request selector 10 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 E2SR Event 2 Service request selector 12 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CCvySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 POSR Period/One match Service request selector 0 1 read-write value1 Forward to CC8ySR0 #00 value2 Forward to CC8ySR1 #01 value3 Forward to CC8ySR2 #10 value4 Forward to CC8ySR3 #11 SWR Interrupt Status Clear 0xB0 32 read-write n 0x0 0xFFFFFFFF RCM1D Channel 1 Compare match while counting down clear 3 write-only RCM1U Channel 1 Compare match while counting up clear 2 write-only RCM2D Channel 2 Compare match while counting down clear 5 write-only RCM2U Channel 2 Compare match while counting up clear 4 write-only RE0A Event 0 detection clear 8 write-only RE1A Event 1 detection clear 9 write-only RE2A Event 2 detection clear 10 write-only ROM One match while counting down clear 1 write-only RPM Period match while counting up clear 0 write-only RTRPF Trap Flag status clear 11 write-only SWS Interrupt Status Set 0xAC 32 read-write n 0x0 0xFFFFFFFF SCM1D Channel 1 Compare match while counting down set 3 write-only SCM1U Channel 1 Compare match while counting up set 2 write-only SCM2D Compare match while counting down set 5 write-only SCM2U Compare match while counting up set 4 write-only SE0A Event 0 detection set 8 write-only SE1A Event 1 detection set 9 write-only SE2A Event 2 detection set 10 write-only SOM One match while counting down set 1 write-only SPM Period match while counting up set 0 write-only STRPF Trap Flag status set 11 write-only TC Slice Timer Control 0x14 32 read-write n 0x0 0xFFFFFFFF CAPC Clear on Capture Control 5 1 read-write value1 Timer is never cleared on a capture event #00 value2 Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event) #01 value3 Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event) #10 value4 Timer is always cleared in a capture event. #11 CCS Continuous Capture Enable 12 read-write value1 The capture into a specific capture register is done with the rules linked with the full flags, described at . #0 value2 The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back). #1 CLST Shadow Transfer on Clear 2 read-write CMOD Capture Compare Mode 3 read-only value1 Compare Mode #0 value2 Capture Mode #1 DIM Dither input selector 15 read-write value1 Slice is using it own dither unit #0 value2 Slice is connected to the dither unit of slice 0. #1 DITHE Dither Enable 13 1 read-write value1 Dither is disabled #00 value2 Dither is applied to the Period #01 value3 Dither is applied to the Compare #10 value4 Dither is applied to the Period and Compare #11 ECM Extended Capture Mode 4 read-write value1 Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only. #0 value2 Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared #1 EME External Modulation Channel enable 27 1 read-write value1 External Modulation functionality doesn't affect any channel #00 value2 External Modulation only applied on channel 1 #01 value3 External Modulation only applied on channel 2 #10 value4 External Modulation applied on both channels #11 EMS External Modulation Synchronization 23 read-write value1 External Modulation functionality is not synchronized with the PWM signal #0 value2 External Modulation functionality is synchronized with the PWM signal #1 EMT External Modulation Type 24 read-write value1 External Modulation functionality is clearing the CC8ySTx bits. #0 value2 External Modulation functionality is gating the outputs. #1 ENDM Extended Stop Function Control 8 1 read-write value1 Clears the timer run bit only (default stop) #00 value2 Clears the timer only (flush) #01 value3 Clears the timer and run bit (flush/stop) #10 FPE Floating Prescaler enable 16 read-write value1 Floating prescaler mode is disabled #0 value2 Floating prescaler mode is enabled #1 MCME1 Multi Channel Mode Enable for Channel 1 25 read-write value1 Multi Channel Mode in Channel 1 is disabled #0 value2 Multi Channel Mode in Channel 1 is enabled #1 MCME2 Multi Channel Mode Enable for Channel 2 26 read-write value1 Multi Channel Mode in Channel 2 is disabled #0 value2 Multi Channel Mode in Channel 2 is enabled #1 SCE Equal Capture Event enable 11 read-write value1 Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #0 value2 Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1 #1 STOS Status bit output selector 29 1 read-write value1 CC8yST1 forward to CCU8x.STy #00 value2 CC8yST2 forward to CCU8x.STy #01 value3 CC8yST1 AND CC8yST2 forward to CCU8x.STy #10 STRM Extended Start Function Control 10 read-write value1 Sets run bit only (default start) #0 value2 Clears the timer and sets run bit, if not set (flush/start) #1 TCM Timer Counting Mode 0 read-write value1 Edge aligned mode #0 value2 Center aligned mode #1 TLS Timer Load selector 7 read-write value1 Timer is loaded with the value of CR1 #0 value2 Timer is loaded with the value of CR2 #1 TRAPE0 TRAP enable for CCU8x.OUTy0 17 read-write value1 TRAP functionality has no effect on the CCU8x.OUTy0 output #0 value2 TRAP functionality affects the CCU8x.OUTy0 output #1 TRAPE1 TRAP enable for CCU8x.OUTy1 18 read-write TRAPE2 TRAP enable for CCU8x.OUTy2 19 read-write TRAPE3 TRAP enable for CCU8x.OUTy3 20 read-write TRPSE TRAP Synchronization Enable 21 read-write value1 Exiting from TRAP state isn't synchronized with the PWM signal #0 value2 Exiting from TRAP state is synchronized with the PWM signal #1 TRPSW TRAP State Clear Control 22 read-write value1 The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW) #0 value2 The TRAP state can only be exited by a SW request. #1 TSSM Timer Single Shot Mode 1 read-write value1 Single shot mode is disabled #0 value2 Single shot mode is enabled #1 TCCLR Slice Timer Clear 0x10 32 read-write n 0x0 0xFFFFFFFF DITC Dither Counter Clear 2 write-only DTC1C Dead Time Counter 1 Clear 3 write-only DTC2C Dead Time Counter 2 Clear 4 write-only TCC Timer Clear 1 write-only TRBC Timer Run Bit Clear 0 write-only TCSET Slice Timer Run Set 0xC 32 read-write n 0x0 0xFFFFFFFF TRBS Timer Run Bit set 0 write-only TCST Slice Timer Status 0x8 32 read-write n 0x0 0xFFFFFFFF CDIR Timer Counting Direction 1 read-only value1 Timer is counting up #0 value2 Timer is counting down #1 DTR1 Dead Time Counter 1 Run bit 3 read-only value1 Dead Time counter is idle #0 value2 Dead Time counter is running #1 DTR2 Dead Time Counter 2 Run bit 4 read-only value1 Dead Time counter is idle #0 value2 Dead Time counter is running #1 TRB Timer Run Bit 0 read-only value1 Timer is stopped #0 value2 Timer is running #1 TIMER Timer Value 0x70 32 read-write n 0x0 0xFFFFFFFF TVAL Timer Value 0 15 read-write UART4 UART 4 UART 0x41307000 0x0 0x14 registers n UART4_TX UART 4 TX 41 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART4_Secure UART 4 (Secure) POSIF 0x51307000 0x0 0x50 registers n HALP Hall Sensor Patterns 0x30 32 read-write n 0x0 0xFFFFFFFF HCP Hall Current Pattern 0 2 read-only HEP Hall Expected Pattern 3 2 read-only HALPS Hall Sensor Shadow Patterns 0x34 32 read-write n 0x0 0xFFFFFFFF HCPS Shadow Hall Current Pattern 0 2 read-write HEPS Shadow Hall expected Pattern 3 2 read-write MCM Multi-Channel Pattern 0x40 32 read-write n 0x0 0xFFFFFFFF MCMP Multi-Channel Pattern 0 15 read-only MCMC Multi-Channel Pattern Control clear 0x4C 32 read-write n 0x0 0xFFFFFFFF MNPC Multi-Channel Pattern Update Enable Clear 0 write-only MPC Multi-Channel Pattern clear 1 write-only MCMF Multi-Channel Pattern Control flag 0x50 32 read-write n 0x0 0xFFFFFFFF MSS Multi-Channel Pattern update status 0 read-only value1 Update of the Multi-Channel pattern is set #0 value2 Update of the Multi-Channel pattern is not set #1 MCMS Multi-Channel Pattern Control set 0x48 32 read-write n 0x0 0xFFFFFFFF MNPS Multi-Channel Pattern Update Enable Set 0 write-only STHR Hall Pattern Shadow Transfer Request 1 write-only STMR Multi-Channel Shadow Transfer Request 2 write-only MCSM Multi-Channel Shadow Pattern 0x44 32 read-write n 0x0 0xFFFFFFFF MCMPS Shadow Multi-Channel Pattern 0 15 read-write MIDR Module Identification register 0x20 32 read-write n 0x0 0xFFFFFF00 MODN Module Number 16 15 read-only MODR Module Revision 0 7 read-only MODT Module Type 8 7 read-only PCONF POSIF configuration 0x0 32 read-write n 0x0 0xFFFFFFFF DSEL Delay Pin selector 16 read-write value1 POSIFx.HSDA #0 value2 POSIFx.HSDB #1 EWIE External Wrong Hall Event enable 26 read-write value1 External wrong hall event emulation signal, POSIFx.EWHE[D...A], is disabled #0 value2 External wrong hall event emulation signal, POSIFx.EWHE[D...A], is enabled. #1 EWIL External Wrong Hall Event active level 27 read-write value1 POSIFx.EWHE[D...A] signal is active HIGH #0 value2 POSIFx.EWHE[D...A] signal is active LOW #1 EWIS Wrong Hall Event selection 24 1 read-write value1 POSIFx.EWHEA #00 value2 POSIFx.EWHEB #01 value3 POSIFx.EWHEC #10 value4 POSIFx.EWHED #11 FSEL Function Selector 0 1 read-write value1 Hall Sensor Mode enabled #00 value2 Quadrature Decoder Mode enabled #01 value3 stand-alone Multi-Channel Mode enabled #10 value4 Quadrature Decoder and stand-alone Multi-Channel Mode enabled #11 HIDG Idle generation enable 4 read-write INSEL0 PhaseA/Hal input 1 selector 8 1 read-write value1 POSIFx.IN0A #00 value2 POSIFx.IN0B #01 value3 POSIFx.IN0C #10 value4 POSIFx.IN0D #11 INSEL1 PhaseB/Hall input 2 selector 10 1 read-write value1 POSIFx.IN1A #00 value2 POSIFx.IN1B #01 value3 POSIFx.IN1C #10 value4 POSIFx.IN1D #11 INSEL2 Index/Hall input 3 selector 12 1 read-write value1 POSIFx.IN2A #00 value2 POSIFx.IN2B #01 value3 POSIFx.IN2C #10 value4 POSIFx.IN2D #11 LPC Low Pass Filters Configuration 28 2 read-write value1 Low pass filter disabled #000 value2 Low pass of 1 clock cycle #001 value3 Low pass of 2 clock cycles #010 value4 Low pass of 4 clock cycles #011 value5 Low pass of 8 clock cycles #100 value6 Low pass of 16 clock cycles #101 value7 Low pass of 32 clock cycles #110 value8 Low pass of 64 clock cycles #111 MCUE Multi-Channel Pattern SW update enable 5 read-write value1 Multi-Channel pattern update is controlled via HW #0 value2 Multi-Channel pattern update is controlled via SW #1 MSES Multi-Channel pattern update trigger edge 21 read-write value1 The signal used to enable a pattern update is active on the rising edge #0 value2 The signal used to enable a pattern update is active on the falling edge #1 MSETS Pattern update signal select 18 2 read-write value1 POSIFx.MSETA #000 value2 POSIFx.MSETB #001 value3 POSIFx.MSETC #010 value4 POSIFx.MSETD #011 value5 POSIFx.MSETE #100 value6 POSIFx.MSETF #101 value7 POSIFx.MSETG #110 value8 POSIFx.MSETH #111 MSYNS PWM synchronization signal selector 22 1 read-write value1 POSIFx.MSYNCA #00 value2 POSIFx.MSYNCB #01 value3 POSIFx.MSYNCC #10 value4 POSIFx.MSYNCD #11 QDCM Position Decoder Mode selection 2 read-write value1 Position encoder is in Quadrature Mode #0 value2 Position encoder is in Direction Count Mode. #1 SPES Edge selector for the sampling trigger 17 read-write value1 Rising edge #0 value2 Falling edge #1 PDBG POSIF Debug register 0x100 32 read-write n 0x0 0xFFFFFFFF HSP Hall Current Sampled Pattern 5 2 read-only IVAL Current Index Value 4 read-only LPP0 Actual count of the Low Pass Filter for POSI0 8 5 read-only LPP1 Actual count of the Low Pass Filter for POSI1 16 5 read-only LPP2 Actual count of the Low Pass Filter for POSI2 22 5 read-only QCSV Quadrature Decoder Current state 0 1 read-only QPSV Quadrature Decoder Previous state 2 1 read-only PFLG POSIF Interrupt Flags 0x70 32 read-write n 0x0 0xFFFFFFFF CHES Correct Hall Event Status 0 read-only value1 Correct Hall Event not detected #0 value2 Correct Hall Event detected #1 CNTS Quadrature CLK Status 10 read-only value1 Quadrature clock not generated #0 value2 Quadrature clock generated #1 DIRS Quadrature Direction Change 11 read-only value1 Change on direction not detected #0 value2 Change on direction detected #1 ERRS Quadrature Phase Error Status 9 read-only value1 Phase Error event not detected #0 value2 Phase Error event detected #1 HIES Hall Inputs Update Status 2 read-only value1 Transition on the Hall Inputs not detected #0 value2 Transition on the Hall Inputs detected #1 INDXS Quadrature Index Status 8 read-only value1 Index event not detected #0 value2 Index event detected #1 MSTS Multi-Channel pattern shadow transfer status 4 read-only value1 Shadow transfer not done #0 value2 Shadow transfer done #1 PCLKS Quadrature Period Clk Status 12 read-only value1 Period clock not generated #0 value2 Period clock generated #1 WHES Wrong Hall Event Status 1 read-only value1 Wrong Hall Event not detected #0 value2 Wrong Hall Event detected #1 PFLGE POSIF Interrupt Enable 0x74 32 read-write n 0x0 0xFFFFFFFF CHESEL Correct Hall Event Service Request Selector 16 read-write value1 Correct Hall Event interrupt forward to POSIFx.SR0 #0 value2 Correct Hall Event interrupt forward to POSIFx.SR1 #1 CNTSEL Quadrature Clock Event Service Request Selector 26 read-write value1 Quadrature Clock Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Clock Event interrupt forward to POSIFx.SR1 #1 DIRSEL Quadrature Direction Update Event Service Request Selector 27 read-write value1 Quadrature Direction Update Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Direction Update Event interrupt forward to POSIFx.SR1 #1 ECHE Correct Hall Event Enable 0 read-write value1 Correct Hall Event interrupt disabled #0 value2 Correct Hall Event interrupt enabled #1 ECNT Quadrature CLK interrupt Enable 10 read-write value1 Quadrature CLK event interrupt disabled #0 value2 Quadrature CLK event interrupt enabled #1 EDIR Quadrature direction change interrupt Enable 11 read-write value1 Direction change event interrupt disabled #0 value2 Direction change event interrupt enabled #1 EERR Quadrature Phase Error Enable 9 read-write value1 Phase error event interrupt disabled #0 value2 Phase error event interrupt enabled #1 EHIE Hall Input Update Enable 2 read-write value1 Update of the Hall Inputs interrupt is disabled #0 value2 Update of the Hall Inputs interrupt is enabled #1 EINDX Quadrature Index Event Enable 8 read-write value1 Index event interrupt disabled #0 value2 Index event interrupt enabled #1 EMST Multi-Channel pattern shadow transfer enable 4 read-write value1 Shadow transfer event interrupt disabled #0 value2 Shadow transfer event interrupt enabled #1 EPCLK Quadrature Period CLK interrupt Enable 12 read-write value1 Quadrature Period CLK event interrupt disabled #0 value2 Quadrature Period CLK event interrupt enabled #1 ERRSEL Quadrature Phase Error Event Service Request Selector 25 read-write value1 Quadrature Phase error Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Phase error Event interrupt forward to POSIFx.SR1 #1 EWHE Wrong Hall Event Enable 1 read-write value1 Wrong Hall Event interrupt disabled #0 value2 Wrong Hall Event interrupt enabled #1 HIESEL Hall Inputs Update Event Service Request Selector 18 read-write value1 Hall Inputs Update Event interrupt forward to POSIFx.SR0 #0 value2 Hall Inputs Update Event interrupt forward to POSIFx.SR1 #1 INDSEL Quadrature Index Event Service Request Selector 24 read-write value1 Quadrature Index Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Index Event interrupt forward to POSIFx.SR1 #1 MSTSEL Multi-Channel pattern Update Event Service Request Selector 20 read-write value1 Multi-Channel pattern Update Event interrupt forward to POSIFx.SR0 #0 value2 Multi-Channel pattern Update Event interrupt forward to POSIFx.SR1 #1 PCLSEL Quadrature Period clock Event Service Request Selector 28 read-write value1 Quadrature Period clock Event interrupt forward to POSIFx.SR0 #0 value2 Quadrature Period clock Event interrupt forward to POSIFx.SR1 #1 WHESEL Wrong Hall Event Service Request Selector 17 read-write value1 Wrong Hall Event interrupt forward to POSIFx.SR0 #0 value2 Wrong Hall Event interrupt forward to POSIFx.SR1 #1 PRUN POSIF Run Bit Status 0x10 32 read-write n 0x0 0xFFFFFFFF RB Run Bit 0 read-only value1 IDLE #0 value2 Running #1 PRUNC POSIF Run Bit Clear 0xC 32 read-write n 0x0 0xFFFFFFFF CRB Clear Run bit 0 write-only CSM Clear Current internal status 1 write-only PRUNS POSIF Run Bit Set 0x8 32 read-write n 0x0 0xFFFFFFFF SRB Set Run bit 0 write-only PSUS POSIF Suspend Config 0x4 32 read-write n 0x0 0xFFFFFFFF MSUS Multi-Channel Mode Suspend Config 2 1 read-write value1 Suspend request ignored #00 value2 Stop immediately. Multi-Channel pattern is not set to the reset value. #01 value3 Stop immediately. Multi-Channel pattern is set to the reset value. #10 value4 Suspend with the synchronization of the PWM signal. Multi-Channel pattern is set to the reset value at the same time of the synchronization. #11 QSUS Quadrature Mode Suspend Config 0 1 read-write value1 Suspend request ignored #00 value2 Stop immediately #01 value3 Suspend in the next index occurrence #10 value4 Suspend in the next phase (PhaseA or PhaseB) occurrence #11 QDC Quadrature Decoder Control 0x60 32 read-write n 0x0 0xFFFFFFFF DVAL Current rotation direction 8 read-only value1 Counterclockwise rotation #0 value2 Clockwise rotation #1 ICM Index Marker generations control 4 1 read-write value1 No index marker generation on POSIFx.OUT3 #00 value2 Only first index occurrence generated on POSIFx.OUT3 #01 value3 All index occurrences generated on POSIFx.OUT3 #10 PALS Phase A Level selector 0 read-write value1 Phase A is active HIGH #0 value2 Phase A is active LOW #1 PBLS Phase B Level selector 1 read-write value1 Phase B is active HIGH #0 value2 Phase B is active LOW #1 PHS Phase signals swap 2 read-write value1 Phase A is the leading signal for clockwise rotation #0 value2 Phase B is the leading signal for clockwise rotation #1 RPFLG POSIF Interrupt Clear 0x7C 32 read-write n 0x0 0xFFFFFFFF RCHE Correct Hall Event flag clear 0 write-only RCNT Quadrature CLK flag clear 10 write-only RDIR Quadrature Direction flag clear 11 write-only RERR Quadrature Phase Error flag clear 9 write-only RHIE Hall Inputs Update Event flag clear 2 write-only RINDX Quadrature Index flag clear 8 write-only RMST Multi-Channel Pattern shadow transfer flag clear 4 write-only RPCLK Quadrature period clock flag clear 12 write-only RWHE Wrong Hall Event flag clear 1 write-only SPFLG POSIF Interrupt Set 0x78 32 read-write n 0x0 0xFFFFFFFF SCHE Correct Hall Event flag set 0 write-only SCNT Quadrature CLK flag set 10 write-only SDIR Quadrature Direction flag set 11 write-only SERR Quadrature Phase Error flag set 9 write-only SHIE Hall Inputs Update Event flag set 2 write-only SINDX Quadrature Index flag set 8 write-only SMST Multi-Channel Pattern shadow transfer flag set 4 write-only SPCLK Quadrature period clock flag set 12 write-only SWHE Wrong Hall Event flag set 1 write-only UART5 UART 5 UART 0x41308000 0x0 0x14 registers n UART5_TX UART 5 TX 125 BAUDDIV Baudrate Divider 0x10 read-write n 0x0 0xFFFFFFFF CTRL UART Control Register 0x8 read-write n 0x0 0xFFFFFFFF HSTX High Speed Test Mode for TX only 6 7 Disable Disabled 0 Enable Enabled 1 RVOVINT RX Overrun Interrupt Enable 5 6 Disable Disabled 0 Enable Enabled 1 RXEN RX Enable 1 2 Disable Disabled 0 Enable Enabled 1 RXINT RX Interrupt Enable 3 4 Disable Disabled 0 Enable Enabled 1 TXEN TX Enable 0 1 Disable Disabled 0 Enable Enabled 1 TXINT TX Interrupt Enable 2 3 Disable Disabled 0 Enable Enabled 1 TXOVINT TX Overrun Interrupt Enable 4 5 Disable Disabled 0 Enable Enabled 1 DATA Receive and Transmit Data Value 0x0 8 read-write n 0x0 0xFFFFFFFF INTCLEAR UART Interrupt CLEAR Register INTSTATUS 0xC write-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 oneToClear RXOV RX Overrun Interrupt 3 4 oneToClear TXINT TX Interrupt 0 1 oneToClear TXOV TX Overrun Interrupt 2 3 oneToClear INTSTATUS UART Interrupt Status Register 0xC read-only n 0x0 0xFFFFFFFF RXINT RX Interrupt 1 2 RXOV RX Overrun Interrupt 3 4 TXINT TX Interrupt 0 1 TXOV TX Overrun Interrupt 2 3 STATE UART Status Register 0x4 read-write n 0x0 0xFFFFFFFF RXBF RX Buffer Full 1 2 read-only RXOV RX Buffer Overun (write 1 to clear) 3 4 oneToClear TXBF TX Buffer Full 0 1 read-only TXOV TX Buffer Overun (write 1 to clear) 2 3 oneToClear UART5_Secure UART 5 (Secure) PORTS 0x51308000 0x0 0x100 registers n HWSEL Port 0 Pin Hardware Select Register 0x74 32 read-write n 0x0 0xFFFFFFFF HW0 Port n Pin Hardware Select Bit 0 0 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW1 Port n Pin Hardware Select Bit 1 2 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW10 Port n Pin Hardware Select Bit 10 20 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW11 Port n Pin Hardware Select Bit 11 22 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW12 Port n Pin Hardware Select Bit 12 24 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW13 Port n Pin Hardware Select Bit 13 26 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW14 Port n Pin Hardware Select Bit 14 28 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW15 Port n Pin Hardware Select Bit 15 30 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW2 Port n Pin Hardware Select Bit 2 4 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW3 Port n Pin Hardware Select Bit 3 6 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW4 Port n Pin Hardware Select Bit 4 8 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW5 Port n Pin Hardware Select Bit 5 10 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW6 Port n Pin Hardware Select Bit 6 12 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW7 Port n Pin Hardware Select Bit 7 14 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW8 Port n Pin Hardware Select Bit 8 16 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 HW9 Port n Pin Hardware Select Bit 9 18 1 read-write value1 Software control only. #00 value2 HW0 control path can override the software configuration. #01 value3 HW1 control path can override the software configuration. #10 IN Port 0 Input Register 0x24 32 read-write n 0x0 0xFFFF0000 P0 Port n Input Bit 0 0 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P1 Port n Input Bit 1 1 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P10 Port n Input Bit 10 10 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P11 Port n Input Bit 11 11 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P12 Port n Input Bit 12 12 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P13 Port n Input Bit 13 13 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P14 Port n Input Bit 14 14 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P15 Port n Input Bit 15 15 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P2 Port n Input Bit 2 2 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P3 Port n Input Bit 3 3 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P4 Port n Input Bit 4 4 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P5 Port n Input Bit 5 5 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P6 Port n Input Bit 6 6 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P7 Port n Input Bit 7 7 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P8 Port n Input Bit 8 8 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 P9 Port n Input Bit 9 9 read-only value1 The input level of Pn.x is 0. #0 value2 The input level of Pn.x is 1. #1 IOCR0 Port 0 Input/Output Control Register 0 0x10 32 read-write n 0x0 0xFFFFFFFF PC0 Port Control for Port n Pin 0 to 3 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC1 Port Control for Port n Pin 0 to 3 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC2 Port Control for Port n Pin 0 to 3 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC3 Port Control for Port n Pin 0 to 3 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR12 Port 0 Input/Output Control Register 12 0x1C 32 read-write n 0x0 0xFFFFFFFF PC12 Port Control for Port n Pin 12 to 15 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC13 Port Control for Port n Pin 12 to 15 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC14 Port Control for Port n Pin 12 to 15 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC15 Port Control for Port n Pin 12 to 15 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR4 Port 0 Input/Output Control Register 4 0x14 32 read-write n 0x0 0xFFFFFFFF PC4 Port Control for Port n Pin 4 to 7 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC5 Port Control for Port n Pin 4 to 7 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC6 Port Control for Port n Pin 4 to 7 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC7 Port Control for Port n Pin 4 to 7 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 IOCR8 Port 0 Input/Output Control Register 8 0x18 32 read-write n 0x0 0xFFFFFFFF PC10 Port Control for Port n Pin 8 to 11 19 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC11 Port Control for Port n Pin 8 to 11 27 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC8 Port Control for Port n Pin 8 to 11 3 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 PC9 Port Control for Port n Pin 8 to 11 11 4 read-write value1 Input - No internal pull device active #00000 value2 Input - Internal pull-down device active #00001 value3 Input - Internal pull-up device active #00010 value4 Input - No internal pull device, Pn_OUTx = input value #00011 value5 Input inverted - No internal pull device active #00100 value6 Input inverted - Internal pull-down device active #00101 value7 Input inverted - Internal pull-up device active #00110 value8 Input inverted - No internal pull device, Pn_OUTx = input value #00111 value9 Output Push-Pull - General-purpose output #10000 value10 Output Push-Pull - Alternate output function 1 #10001 value11 Output Push-Pull - Alternate output function 2 #10010 value12 Output Push-Pull - Alternate output function 3 #10011 value13 Output Push-Pull - Alternate output function 4 #10100 value14 Output Open Drain - General-purpose output #11000 value15 Output Open Drain - Alternate output function 1 #11001 value16 Output Open Drain - Alternate output function 2 #11010 value17 Output Open Drain - Alternate output function 3 #11011 value18 Output Open Drain - Alternate output function 4 #11100 OMR Port 0 Output Modification Register 0x4 32 read-write n 0x0 0xFFFFFFFF PR0 Port n Reset Bit 0 16 write-only PR1 Port n Reset Bit 1 17 write-only PR10 Port n Reset Bit 10 26 write-only PR11 Port n Reset Bit 11 27 write-only PR12 Port n Reset Bit 12 28 write-only PR13 Port n Reset Bit 13 29 write-only PR14 Port n Reset Bit 14 30 write-only PR15 Port n Reset Bit 15 31 write-only PR2 Port n Reset Bit 2 18 write-only PR3 Port n Reset Bit 3 19 write-only PR4 Port n Reset Bit 4 20 write-only PR5 Port n Reset Bit 5 21 write-only PR6 Port n Reset Bit 6 22 write-only PR7 Port n Reset Bit 7 23 write-only PR8 Port n Reset Bit 8 24 write-only PR9 Port n Reset Bit 9 25 write-only PS0 Port n Set Bit 0 0 write-only PS1 Port n Set Bit 1 1 write-only PS10 Port n Set Bit 10 10 write-only PS11 Port n Set Bit 11 11 write-only PS12 Port n Set Bit 12 12 write-only PS13 Port n Set Bit 13 13 write-only PS14 Port n Set Bit 14 14 write-only PS15 Port n Set Bit 15 15 write-only PS2 Port n Set Bit 2 2 write-only PS3 Port n Set Bit 3 3 write-only PS4 Port n Set Bit 4 4 write-only PS5 Port n Set Bit 5 5 write-only PS6 Port n Set Bit 6 6 write-only PS7 Port n Set Bit 7 7 write-only PS8 Port n Set Bit 8 8 write-only PS9 Port n Set Bit 9 9 write-only OUT Port 0 Output Register 0x0 32 read-write n 0x0 0xFFFFFFFF P0 Port n Output Bit 0 0 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P1 Port n Output Bit 1 1 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P10 Port n Output Bit 10 10 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P11 Port n Output Bit 11 11 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P12 Port n Output Bit 12 12 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P13 Port n Output Bit 13 13 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P14 Port n Output Bit 14 14 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P15 Port n Output Bit 15 15 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P2 Port n Output Bit 2 2 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P3 Port n Output Bit 3 3 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P4 Port n Output Bit 4 4 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P5 Port n Output Bit 5 5 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P6 Port n Output Bit 6 6 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P7 Port n Output Bit 7 7 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P8 Port n Output Bit 8 8 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 P9 Port n Output Bit 9 9 read-write value1 The output level of Pn.x is 0. #0 value2 The output level of Pn.x is 1. #1 PDISC Port 0 Pin Function Decision Control Register 0x60 32 read-write n 0x0 0xFFFF0000 PDIS0 Pad Disable for Port n Pin 0 0 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS1 Pad Disable for Port n Pin 1 1 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS10 Pad Disable for Port n Pin 10 10 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS11 Pad Disable for Port n Pin 11 11 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS12 Pad Disable for Port n Pin 12 12 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS13 Pad Disable for Port n Pin 13 13 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS14 Pad Disable for Port n Pin 14 14 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS15 Pad Disable for Port n Pin 15 15 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS2 Pad Disable for Port n Pin 2 2 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS3 Pad Disable for Port n Pin 3 3 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS4 Pad Disable for Port n Pin 4 4 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS5 Pad Disable for Port n Pin 5 5 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS6 Pad Disable for Port n Pin 6 6 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS7 Pad Disable for Port n Pin 7 7 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS8 Pad Disable for Port n Pin 8 8 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDIS9 Pad Disable for Port n Pin 9 9 read-only value1 Pad Pn.x is enabled. #0 value2 Pad Pn.x is disabled. #1 PDR0 Port 0 Pad Driver Mode 0 Register 0x40 32 read-write n 0x0 0xFFFFFFFF PD0 Pad Driver Mode for Pn.0 0 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD1 Pad Driver Mode for Pn.1 4 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD2 Pad Driver Mode for Pn.2 8 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD3 Pad Driver Mode for Pn.3 12 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD4 Pad Driver Mode for Pn.4 16 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD5 Pad Driver Mode for Pn.5 20 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD6 Pad Driver Mode for Pn.6 24 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD7 Pad Driver Mode for Pn.7 28 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PDR1 Port 0 Pad Driver Mode 1 Register 0x44 32 read-write n 0x0 0xFFFFFFFF PD10 Pad Driver Mode for Pn.10 8 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD11 Pad Driver Mode for Pn.11 12 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD12 Pad Driver Mode for Pn.12 16 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD13 Pad Driver Mode for Pn.13 20 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD14 Pad Driver Mode for Pn.14 24 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD15 Pad Driver Mode for Pn.15 28 2 read-write sd_soe_alt A1+ strong driver, soft edge (alternate value) #000 sd_sle_alt A1+ strong driver, slow edge (alternate value) #001 sd_soe A1+ strong driver, soft edge #010 sd_sle A1+ strong driver, slow edge #011 md A1+ medium driver #100 wd_alt A1+ weak driver (alternate value) #101 md_alt A1+ medium driver (alternate value) #110 wd A1+ weak driver #111 PD8 Pad Driver Mode for Pn.8 0 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PD9 Pad Driver Mode for Pn.9 4 2 read-write sd_she A2 strong driver, sharp edge #000 sd_mee A2 strong driver, medium edge #001 sd_soe A2 strong driver, soft edge #010 md A2 medium driver #100 wd A2 weak driver #111 PPS Port 0 Pin Power Save Register 0x70 32 read-write n 0x0 0xFFFFFFFF PPS0 Port n Pin Power Save Bit 0 0 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS1 Port n Pin Power Save Bit 1 1 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS10 Port n Pin Power Save Bit 10 10 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS11 Port n Pin Power Save Bit 11 11 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS12 Port n Pin Power Save Bit 12 12 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS13 Port n Pin Power Save Bit 13 13 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS14 Port n Pin Power Save Bit 14 14 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS15 Port n Pin Power Save Bit 15 15 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS2 Port n Pin Power Save Bit 2 2 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS3 Port n Pin Power Save Bit 3 3 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS4 Port n Pin Power Save Bit 4 4 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS5 Port n Pin Power Save Bit 5 5 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS6 Port n Pin Power Save Bit 6 6 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS7 Port n Pin Power Save Bit 7 7 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS8 Port n Pin Power Save Bit 8 8 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 PPS9 Port n Pin Power Save Bit 9 9 read-write value1 Pin Power Save of Pn.x is disabled. #0 value2 Pin Power Save of Pn.x is enabled. #1 WATCHDOG Non-secure Watchdog Timer WATCHDOG 0x40081000 0x0 0xC04 registers n NONSEC_WATCHDOG_IRQ Non-Secure Watchdog Interrupt 1 WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF WATCHDOG_Secure Watchdog (Secure) WATCHDOG 0x50081000 0x0 0xC04 registers n WDOGCONTROL Watchdog Control Register 0x8 read-write n 0x0 0xFFFFFFFF INTEN Enable the interrupt event 0 1 Disable Disable Watchdog interrupt 0 Enable Enable Watchdog interrupt. 1 RESEN Enable watchdog reset output 1 1 Disable Disable Watchdog reset 0 Enable Enable Watchdog reset 1 WDOGINTCLR Watchdog Interrupt Clear Register 0xC write-only n 0x0 0xFFFFFFFF INT Interrupt 0 1 oneToClear WDOGLOAD Watchdog Load Register 0x0 read-write n 0xFFFFFFFF 0xFFFFFFFF WDOGLOCK Watchdog Lock Register 0xC00 read-write n 0x0 0xFFFFFFFF Access Enable register writes 1 31 Status Register write enable status 0 1 Enabled Write access to all other registers is enabled. This is the default. 0 Disabled Write access to all other registers is disabled. 1 WDOGMIS Watchdog Mask Interrupt Status Register 0x14 read-only n 0x0 0xFFFFFFFF MIS Masked Watchdog Interrupt 0 1 WDOGRIS Watchdog Raw Interrupt Status Register 0x10 read-only n 0x0 0xFFFFFFFF RIS Raw watchdog Interrupt 0 1 WDOGVALUE Watchdog Value Register 0x4 read-only n 0xFFFFFFFF 0xFFFFFFFF